SU255656A1 - COMPUTATIONAL DEVICE FOR PROCESSING NUMERICAL AND LETTER INFORMATION - Google Patents

Description

The invention relates to the field of computing, in particular, to the structure of digital computers using problem-oriented algorithmic languages.

A computing device for processing numerical and alphabetic information in a machine with a high level of interpretation of problem-oriented algorithmic languages is known, which contains an adder, a buffer AND shift register, a result register and a control unit.

The proposed device differs from the known ones in that it contains a register of types of operands, the input circuits of which are connected to the central control unit and the output to the local control unit for automatic conversion of the types of operands and the formation of the result jwua; an automaton for generating and memorizing hyphenation for performing addition over components of operands of higher order, the input circuits of which are connected to the higher order and the output circuits to the younger end of the mantissary adder; automatic control of the placement of operands. in the registers of the arithmetic unit, the input circuits of which are connected with the central control unit, and the output circuits - with the control unit; control counter for string-code operations,

the input circuits of the latter are connected via the switching circuits of the control unit during execution of operations to the fields of lines and codes and to the buffer register, the output circuits of the control counter are connected to the local control unit; a comparison circuit whose input circuits are connected to the register of orders, and the output circuits are connected to the control unit; an inverter unit for transmitting the forward, inverse, and shifted code of the second operand to the adder, and its input circuits are connected to the outputs of the second operand register triggers, and the output circuits to the inputs of the adder; a block of additional triggers of operand characters and a result character, connected to the register of operands.

This allows you to perform entered to simplify programming and enhancement

efficiency of the interpretation of operations on codes, strings, integers, real and complex numbers, with any combination of these operands, including real and complex numbers of arbitrary length, and

also receive high speed and maximize the use of equipment.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a block diagram of the Device consists of three 48-bit shift registers / 2 and 5 and a buffer register 4 combining the execution of a given operation in a computing device with a sample of a new operand from the memory. Register 1 is the result register and output wired is connected to the memory. All registers are interconnected to transfer operands from one register to another. The registers Y and 5 are connected by common shift chains, uniting them into one 96-bit register for performing 48-bit word shift operations while preserving bits that went beyond the limits of the grid grid and for performing the operation in lines and codes. in cases where the string or code field is located in two memory locations. The orders of operands represented as floating point numbers are located in 8 bits of registers (the 8th bit is the sign of the order), the remaining 40 bits contain the mantissa of the operands (the 40th bit is the sign of the mantissa). The operands, represented as a fixed fraction with a fixed comma or as integers, are located in the bits assigned to the mantis. One-lines of the type “line and code occupy 48 bits in the registers of a computing device. Register 1 and directly output buses, and register 2 through blocks 5 and 6 of inverters are connected with a parallel combiner 7 times, an adder 8 mantis. These two summators are combined by a common carry chain only to perform processing of strings and codes, in the remaining cases these are two independent adders with their own cyclic carry prices. In order to break the cyclic transfer chain in the adder 8, in the case of an operation with increased accuracy, the cyclic transfer memory automatic machine 9 is used, which is connected by the output busses with the least significant amount of the mantissary adder. Adders 7 and S are associated with the result register 1. A further reduction of the summation time in comparison with the prototype was achieved by introducing the block 10 of the analysis of the operands. The unit 10 by the output busbars is connected to the local control unit // to generate a summing up signal. Blocks 5 and 5 of the inverters are inserted to obtain the forward, inverse, and shift of the operand code located in register 2. The output busbars of the inverter unit is connected to the adder. The introduction of this block made it possible to reduce the summation time due to the absence of additional time for wrapping the code of the second operand and by freeing the inputs of the adder, which are used to organize the scheme of transfer acceleration. The shifted code of the second operand, obtained in block 6, is used to accelerate the multiplication operation (multiplication is performed starting from the lower multiples of the multiplier, analyzing the two multiples of the multiplier, adding the forward, reverse, or direct shifted multiplicative code to the partial product and shifting multiplier by two). Arithmetic operations are performed on unsigned operands (the sign bits of the registers 1, 2 W. 4 are set to the zero state before performing arithmetic operations). The characters of the operands are memorized in block 12, in the same block a result of arithmetic operations is formed, which is transmitted to the sign bit of the result register after the operation is performed. The introduction of this block allowed for performing arithmetic operations to use the reverse code only of the second operand, regardless of the sign of the first operand. When adding and subtracting, the reverse code of the second operand is used if the sum of mod 2 characters of two operands is equal to one (the subtraction operations are replaced by the addition operation decremented with the subtracted, the sign of which changes to the opposite in block 12). In contrast to the prototype of the operations for zero-accessing a string or code, and the operation of character-by-character processing of strings are performed on computing device blocks, processing and numerical information. The operations of referring to the fields of strings and codes allow the sampling of codes or characters from the TERROR FIELD or writing new values of code positions or characters to the field. To control these operations, a counter 13 is introduced for controlling line-code operations. String character processing operations allow the movement and replacement of characters within a string. Reversal to fields is performed using the operations of linear, cyclic, and character (8 bits) shifts carried out in numerical ones. device registers where processed codes and strings are located. Character processing of strings is carried out in an arithmetic unit of 14 orders, where characters are compared and, depending on the result of the comparison, the symbol is replaced with the string being processed. The // local control unit (Fig. 2) consists of an automatic control unit 15, a micro-operation unit 16, a register of 17 operations, a register / 8 types of operands, two 8-bit Counters 19 and 20. The execution of any operation starts with the installation of a trigger for the corresponding operation in the operation register by the signal from the central device and the launch of the corresponding firmware of the control unit. The sequence of micro-operations corresponding to this firmware, producing micro-operations registers of the arithmetic unit. Unlike the prototype, each operand enters the calculating device together with the type of the operand. The type of the operand indicates whether the operand is represented as a floating point number, as a regular fraction with a fixed comma, as a string or as a code. The type of the operand is stored in the register of the 18 types of operands and is used 10 as the condition for determining the branch of the microprogram in the control unit and for determining the type of result. When performing arithmetic operations, a combination of different types of operands is allowed, with 15, if one of the operands is represented as a floating point number or operaids are of different types, the result will be represented as a floating-point number, and the operands are automatically reduced to 20 tiiu floating point numbers. If the types of the two operands are the same, the arithmetic operations on them are performed in accordance with the arithmetic rules for floating-point numbers (for floating-point operands) or in accordance with the rules of fixed-point arithmetic (for operands presented in the form of a regular fraction with a fixed comma or As integers and codes) .30 Structural Interpretation of the language in the mask leads to the necessity of direct and inverse operations. During the return operation, the order of the operands in the computing device 35 is reversed. To specify the order of the operands, which is important when performing non-commutative operations, an automaton 21 is introduced. According to the state of this automaton, for non-commutative operations it is performed 40 before performing the operation, the operands are moved to the desired registers of the arithmetic unit. Thus, the proposed device performs; a) arithmetic operations like addition, subtraction, multiplication, division (each of these operations has four modifications; with rounding — with normalization. without rounding — with normalization, with rounding — 50, without normalization, without rounding, without normalization), addition and subtracting the moduli of numbers, adding the 48-bit words for the operands, represented as floating-point numbers, the fixed rec-55 of that, integers, operands of type code and type of string; b) logical operations like disjunction, conjunction, equivalence, implication, negation over Boolean operands and bo code type operands; c) operations of the relation type "more," less, "equal," not equal, "not. more," not less for the types of operands listed in clause a; 65 45 g) operations of converting one type of operands to another for numbers; e) operations of shifts of a 48-bit word or mantissa without a ziac (left, right, cyclic and non-cyclic on a const or up to the gth unitary code position); e) - counting operations of the number of zero or unit code points (right, left), search operations of a given zero or unit code position; g) operations to zero a string or code (for sampling a field or for writing to a field); h) operation of writing a line processing (unconditional and conditional symbol replacement, character comparison); i) the operation of assembling and disassembling strings and codes by masks; j) adding mantissas with remembering the transfer from the cTapaiero bit to perform arithmetic operations on real and complex numbers of arbitrary length. The performance of the entire listed set of operations is provided by the proposed parallel arithmetic unit and local control unit, and as can be seen from the above description, it is sufficiently relatively simple circuit means. Subject of the Invention A computing device for processing numeric and alphabetic information in a machine with a high level of interpretation of problem-oriented algorithmic languages, containing an adder, a buffer and shift registers, a result register and a control unit, characterized in that, in order to execute entered for ease of programming and enhancement the efficiency of interpretation of the operation over codes, strings, targets, and, real and complex numbers: gi, for any combination of these operands, including valid In addition, to obtain high speed and maximum use of equipment, it contains a register of types of operands, the input circuits of which are connected with a central control device, and the output with a local control unit for automatic conversion of types of operations and education. type of result; automating the formation and memorization of hyphenation to perform the addition over the components of the higher-order ramps, whose input circuits are connected to the upper row and the output to the younger bit of the mantissary adder; the automatic control unit, the placement of operands in the registers of the arithmetic unit, the input circuits are connected to the central paging device, and the output circuits are connected to the control unit, the control counter for the line-code ogs, and the input circuits of the latter

connected through the switching circuits of the control unit during the execution of operations to the fields of the string and the codes to the buffer register, the output circuits of the control counter are connected to the local control unit; the comparison circuit, the input circuits of which are connected to the register of orders, and the output circuits - with the control unit, inverters

to transmit the forward, inverse, and shifted code of the second operand to the adder, with its input circuits connected to the outputs of the second operand register triggers, and the output circuits to the inputs of the adder; a block of additional triggers of operand characters and a result character, connected to the register of operands.

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