RU2686628C1 - Addition-subtraction device for digital signal processor - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to digital data processing devices. Device comprises first unit of conditional selection of minor part of mantissas, second unit for conditional selection of upper part of mantissas, unit for selection of maximum exponential part of two operands, unit for difference of exponentials, unit of absolute value of difference, unit of unit adding, unit of shift of mantissa, two units of formation of value of saturation, unit of formation of inverse code, unit of subtraction of double format, three units of conditional transition.

EFFECT: technical result is simple design and faster operation during asynchronous data exchange.

1 cl, 2 dwg

Description

The invention relates to digital data processing devices and can be used as an IP block for digital-signal processors.

Known devices for performing various arithmetic operations in the format of floating-point numbers.

From US patent US5487022, normalization of the exponential part of the number is known by means using decoders, memory, logic elements, multiplexers. Means are implemented in the form of an integrated device, characterized by high hardware costs.

A device for operational multiplication with a floating point (US patent application US20150347089) is known. To perform the multiplication operation, blocks of normalization of numbers are introduced into the device, which excessively perform equivalent functions, which complicates the construction.

US patent US6516332 discloses a device for performing mathematical operations on numbers in floating point format. This device allows to perform addition, subtraction, multiplication, division operations on numbers, and is built on a processor base for floating point operations. The device contains a microcontroller, a microcontroller memory block, a gate array, a set of floating-point operator modules for performing mathematical operations of addition, subtraction, multiplication and division, each of which includes an adder, a subtractor, a multiplier and a divider, the first multiplexer for receiving data from the adder and subtractive device, a second multiplexer for receiving data from a multiplier and a divider, and a third multiplexer for receiving relevant data from the first and second multiplex sors. The disadvantage of this device is that the fixed value (bit depth) of the mantissa and the exponent limit its scope, and it itself is intended to control motors.

The closest analogue of the claimed invention is a device with a floating point for addition-subtraction according to US patent US5568412. This device includes an alignment scheme, an addition-subtraction and rounding scheme, and a normalization scheme. The alignment circuit aligns the parts of the first and second operands based on the difference of their samples. The addition-subtraction and rounding scheme performs at least two addition-subtraction between the aligned parts of the first and second operands and selectively produces the value of the result of one of the rounded results of the addition / subtraction of the parts of the first and second operands. The normalization scheme normalizes the result, rounded off from the value, to produce the final result of addition / subtraction of parts. These three device circuits are based on a comparator, a first and a second adder, an alignment circuit, paging schemes, the first XOR gate, the AND gate, the OR gate set, the half combinator circuit, two multiplexers, and an initial counter zero converter. The device requires synchronous data exchange between its functional nodes and has insufficient speed.

Like previous devices, the device-analogue is characterized by high hardware costs.

The present invention is to eliminate the disadvantages of the known devices of addition and subtraction of numbers, the improvement of their technical and operational characteristics.

The technical result consists in simplifying the design and improving the speed of the device for adding and subtracting numbers during asynchronous data exchange.

The problem is solved, and the claimed technical result is achieved in the device of addition and subtraction of numbers for the digital-signal processor, which contains the first conditional selection block of the younger part of the mantissas, the second conditional choice block of the older part of the mantissas, the maximum choice block of the exponential part of two operands, the difference unit of exponential parts, absolute difference unit, unit addition unit, mantissa shift unit, first saturation value generating unit, second saturation value forming unit, formation unit I have an inverse code, a double format subtraction unit, the first, second and third conditional block. The first input of the first conditional selection block of the lower part of the mantissa serves to receive the lower level of the mantissa of the first number, its second input to receive the lower level of the mantissa of the second number, its third input to the arrival of the first exponent, its fourth input to the second exponent. The first input of the second block of conditional selection of the older part of the mantissa serves for the arrival of the older part of the mantissa of the first number, and its second input is for the arrival of the older part of the mantissa of the second number. The third input and the fourth input of the first conditional selection unit of the lower part of the mantis are connected respectively to the third input and the fourth input of the second conditional selection unit of the older part of the mantissa. The third input and the fourth input of the first conditional selection block of the lower part of the mantis are connected respectively to the first input and the second input of the maximum selection block of the exponential part of two operands. The third input and the fourth input of the first conditional selection block of the lower part of the mantis are connected to the first input and the second input of the difference block of the exponents, respectively. The first output of the first conditional selection block of the younger part of the mantis is connected to the first inputs of the first block and the second block of formation of the saturation value. The second output of the first conditional block of the younger part of the mantis is connected to the first input of the mantissa shift block. The first output of the second conditional selection block of the lower part of the mantis is connected respectively to the second input of the first block of formation of the saturation value and the second input of the second block of formation of the saturation value. The second output of the second conditional block of the younger part of the mantis is connected to the second input of the shift block of the mantissa. The output of the maximum selection block of the exponential part of the two operands is connected to the input of the unit for adding one and the first input of the third conditional branch. The output of the unit addition unit is connected to the second input of the third conditional block. The output of the exponent of the difference block is connected to the input of the absolute value of the difference block, the output of which is connected to the third input of the shift mantissa block. The first output of the shift block mantissa is connected to the third inputs of the first and second blocks of formation of the saturation value. The second output of the shift block mantissa is connected to the fourth inputs of the first and second blocks of formation of the saturation value. The first output of the first block of formation of the saturation value is connected to the first input of the block of formation of the inverse code and the first input of the second block of conditional transition. The second output of the first block of formation of the saturation value is connected with the second input of the block of formation of the inverse code, with the first and third inputs of the first conditional transfer unit, with the third input of the second conditional transfer unit and the third input of the third conditional transfer unit. The output of the second block of formation of the saturation value is connected to the fourth inputs of the first, second and third blocks of the conditional transition. The first and second outputs of the inverse code generation unit are respectively connected to the first and second inputs of the double format subtraction unit, the first output of which is connected to the second input of the second conditional transfer unit, and the second output to the second input of the first conditional transfer unit. The outputs of the first, second and third blocks of the conditional transition serve as outputs of the higher-order mantissa, the lower-order mantissa, and the addition and subtraction exponential numbers.

The advantages as well as the features of the present invention are explained using an embodiment of the invention with reference to the figures.

FIG. 1 shows a functional diagram of the claimed device;

FIG. 2 shows the general format of a floating-point number.

FIG. 1 marked the following positions:

1 - the first conditional selection block of the younger part of mantis

2 - the second block of conditional selection of the older part of mantis

3 - block selection of the maximum exponential part of the two operands

4 - exponent difference block

5 - the block of the absolute value of the difference

6 - unit addition unit

7 - mantissa shift block

8 - the first block forming the value of saturation

9 - the second block forming the value of saturation

10 - block the formation of the inverse code

11 - double format subtraction unit

12, 13, 14 - the first, second and third blocks of the conditional transition, respectively

15, 16, 17, 18 - inputs (input buses) of these numbers

19–37 - bus connections

38, 39, 40 - outputs (output buses) of these numbers.

Glossary of terms used in the description and figures:

Add - addition

Cond - condition

Exp - Exhibitor

Mant - mantissa

Shift - shift operation

Sub - subtraction

Cnd1 - condition block 1

Cnd2 - condition block 2

Shmant - mantissa shift block

Maxexp - maximum exponent

Exp1 - block of formation of the absolute value of the exponent of the result

FP - floating point format

IP block (I-PI block) - complete functional device

Minus - minus or subtract.

The addition-subtraction device for the processor (Fig. 1) contains the first conditional selection block 1 of the lower part of the mantis, the second conditional selection block 2 of the higher part of the mantissa, the maximum selection block 3 of the exponential part of two operands, the difference exponent 4, the absolute difference value 5, unit 6 addition unit, the mantissa shift unit 7, the first saturation value generation unit 8, the second saturation value generation unit 9, the inverse code generation unit 10, the double format subtraction unit 11, the first conditional transition unit 12, volts The block 13 conditional transition and the third block 14 conditional transition. The first input 15 of the first block 1 of the conditional selection of the lower part of the mantis serves to receive the low order of the mantissa of the first number, its second input 16 to receive the low order of the mantissa of the second number, its third input 17 to receive the first exponential, its fourth input 18 to arrivals of the exponent of the second number. The first input 19 of the second unit 2 of the conditional selection of the older part of the mantissa serves to receive the older part of the mantissa of the first number, and its second input 20 to receive the older part of the mantissa of the second number. The third input 17 and the fourth input 18 of the first block 1 of the conditional selection of the younger part of the mantis are connected respectively to the third input and the fourth input of the second block 2 of the conditional choice of the older part of the mantissas. The third input 17 and the fourth input 18 of the first block 1 of the conditional selection of the lower part of the mantis are connected respectively to the first input and to the second input of the maximum selection block 3 of the exponential part of two operands. The third input 17 and the fourth input 18 of the first block 1 of the conditional selection of the younger part of the mantis are connected respectively to the first input and to the second input of the block 4 of exponential differences. The first output of the first block 1 conditional selection of the younger part of the mantissa is connected to the first inputs of the first block 8 and the second block 9 of the formation of the saturation value. The second output of the first block 1 conditional selection of the younger part of the mantissa is connected to the first input of the block 7 of the shift of the mantissa. The first output of the second unit 2 conditional selection of the younger part of the mantissa is connected respectively with the second input of the first block 8 forming the saturation value and with the second input of the second block 9 forming the saturation value. The second output of the second unit 2 conditional selection of the older part of the mantissa is connected to the second input of the block 7 of the shift of the mantissa. The output of the maximum selection block 3 of the exponential part of the two operands is connected to the input of the unit 6 for adding one and to the first input of the third conditional transition block 14. The output of the node 6 of the addition of the unit is connected to the second input of the third block 14 conditional transition. The output of block 4 of the difference of the exponents is connected to the input of the block 5 of the absolute value of the difference, the output of which is connected to the third input of the block 7 of the shift of the mantissa. The first output of the mantissa shift block 7 is connected to the third inputs of the first and second saturation value generating units 8, 9, the second output of the mantissa shift unit 7 is connected to the fourth inputs of the first and second saturation value generating units 8, 9. The first output of the first block 8 forming the saturation value is connected with the first input of the block 10 of the formation of the inverse code and with the first input of the second block 13 conditional transition. The second output of the first block 8 forming the saturation value is connected with the second input of the block 10 forming the inverse code, with the first and the third input of the first block 12 conditional transition, with the third input of the second block 13 conditional transition and with the third input of the third block 14 conditional transition. The output of the second block 9 of forming the saturation value is connected to the fourth inputs of the first block 12 of the conditional transition, the second block 13 of the conditional transition and the third 14 block of the conditional transition. The first and second outputs of the inverse code generation unit 10 are respectively connected to the first and second inputs of the double format subtraction unit 11, the first output of which is connected to the second input of the second conditional transfer unit 13, and the second output to the second input of the first conditional transfer unit 12. The outputs 38, 39, 40, respectively, of the first conditional transition unit 12, the second conditional transition unit 13, and the third conditional transition unit 14 serve as outputs of the higher-order mantissa, the lower-order mantissa, and the addition and subtraction exponential numbers.

The claimed device works as follows.

The inputs 15, 16, 17, 18, 19, 20 receive signals from the mantis (the high and low bits) and the exponentials of the two operands.

The operation performed in the claimed device is the addition or subtraction of operands. Unlike the closest analogue, to perform these operations, calculations are performed depending on the state of the tires 29 and 30 in the first and second blocks 8, 9 of the formation of the saturation value only, the second block 9 of the formation of the saturation value of the blocks 8 and 9 (for addition or subtraction ).

For the correct execution of operations, it is necessary to match the exponential parts of the two operands. In this regard, these functions are more complex for formats such as addition and subtraction than for performing the multiplication operation. The coordination of the exponential parts of the operands is performed by block 3 of selecting the maximum of the exponential part of two operands, by block 4 of the differences of exponentials, by block 5 of the absolute value of the difference, by node 6 of the addition of one.

The conditional selection block 1 of the lower part of the mantissa is designed to form the first and second outputs or the second and first outputs of the first and second operands, respectively (the lower part of the operand mantissa), depending on whose exponential part is larger. It works as a conditional switch. Similarly, the appointment for the block 2 conditional selection of the mantissa (senior part). Block 3 of the maximum of the exponential part of the operands is designed to compare these values and select the maximum part of the two exponentials. Block 4 forms the difference of the exponentials of the two operands (exp1 - exp2), and then block 6 forms the absolute value of this value. The mantissa shift block 7 provides a programmable mantissa shift (in the senior and junior parts) for the number of bits that comes from the output of block 6. The blocks 8 and 9 for forming saturation values are designed to determine the maximum value of the mantissa, if it exceeds the maximum value during shift operations , for example, 1111 ... 1. The first and second blocks of the conditional transition 12 and 13 are designed to form the final size of the mantissa (the older and younger parts). The third block of conditional transition 14 is intended for the final formation of the exponential part of the result.

Bus 25 maximum exponent of the two operands, increased by 1 (if necessary, normalization) receives the second input of the block 14 conditional transition. Wherein the first input unit 14 is a conditional branch from block 3 outputs the exponent of the maximum selecting two operands received maximum value of exponent without upgrading (e.g., 2 ³ and 2 ⁵ - are selected February ^5). In block 14, the choice between these two quantities is made depending on the signals on buses 31 and 33. If these signals are equal (normalization is not required), then the exponent generated on bus 27 is transferred to output 40, otherwise information from bus 25 is output. 38 and 39 the upper and lower parts of the mantissa are formed. Mantissa is a 32-bit word, respectively, on the bus 16 bits.

The common format F of a floating point number is shown in FIG. 2:

F = (-1) ^S · M · β ^E ,

where S is the sign of the number: S = 0 is a positive number, S = 1 is a negative number; M - mantissa - the fractional part of the number; β is the base part of the exponent; Е - degree of exponent.

On tires 21, 22, 23 and 24, the junior and senior components of the mantis are formed depending on the exponent values of the incoming operands, for example, from input 15 to bus 21 or bus 22 and from input 16 to bus 22 or bus 21; similarly, from input 19 to bus 23 or bus 24, and from input 20 to bus 24 or bus 23. Thus, depending on the values of the numbers (which is more or less), numbers are transferred to the corresponding outputs - bus 21 or 22, and 23 or 24. The shift value of the 32-bit mantissa is carried out in the shift block 7 and is determined by the absolute value of the exponent difference (for example, a difference of 4 means a shift by two digits - 2 ² = 4), coming through the bus 26. At that, This format is shown below:

Minimum (absolute value) = 2,328306436538696 · 10 ^-10 (excluding the “0”);

Maximum (absolute value) = 2 ³²⁷⁶⁸ ;

Maximum negative value in absolute value = -2 ^-65536 · 2 ^-31 ;

Minimum = -2 ³²⁷⁶⁸ .

In the first and second blocks 8, 9 of the formation of the saturation value, an addition or subtraction operation is performed depending on the command code. In this case, the values are formed taking into account the maximum value - saturation (saturation): for example, the maximum value of a positive number or the maximum value of the absolute value of a negative number is 0.1111 ... 1 or 1.0000 ... 0, respectively.

To form a negative number, the device includes an inverse code block 10 and a double-format subtractor 11, in which the inverse value of the selected mantissa is subtracted from 7fff ffff (hexagonal representation of the number), where the 12 and 13 conditional transition blocks are then depending on the signal state (“0 "Or" 1 ") on tires 33, 36 and 32, 37 for each of them form the output mantissa of the result.

The device is built on an asynchronous principle, therefore, time diagrams and critical circuits (with variation of parameters) do not affect its performance. The device is completely autonomous and can be used as an IP block for digital-signal processors with a fixed decimal point, in which, for example, it is necessary to perform operations with a floating point. The claimed technical result, which consists, inter alia, in simplifying the design and improving performance in asynchronous data exchange, is achieved by applying a new functional circuit shown in FIG. 1, with a new working principle.

In the specific functional diagram shown, each block operates in a 16- or 32-bit format. The autonomy of the blocks can also be ensured by the presence of a FIFO buffer (in particular, a small size) at the input and output of the circuit. The size of this memory is determined by the general structure of the digital-signal processors and the choice of the command system. The depth of the FIFO may be, for example, 8–16 words. In general, the proposed technical solution allows to effectively implement the functional requirements for digital-signal processes. Buffer memory (buffer memory) at the request of the developer allows you to store a sequence of input data and the result of the dependence on the implemented device.

The most successfully declared device is the addition and subtraction of numbers for the digital-signal processor is industrially applicable in the IP blocks of digital-signal processors with a fixed comma, in which it is necessary to carry out operations with a floating point for various digital data processing equipment.

Claims (8)

An addition-subtraction device for a processor, containing the first conditional selector unit of the lower part of the mantis, the second conditional selector unit of the older part of the mantissa, the maximum selection unit of the exponential part of two operands, the exponent difference unit, the unit of absolute difference value, the unit of unit addition, the shift unit of the mantissa, the first block forming the value of saturation, the second block forming the value of saturation, block forming the inverse code, block subtraction double format, the first conditional block, the second unit conditional transition and third conditional branch unit, the first input of the first conditional selection block of the lower part of the mantissa serves for the entry of the lower order of the mantissa of the first number, its second input for the receipt of the lower order of the mantissa of the second number, its third entrance for the arrival of the first exponent, its fourth input for the arrival of the second numbers the first input of the second conditional block of the senior part of the mantissa serves for the arrival of the senior part of the mantissa of the first number, and its second input - for the receipt of the senior part of the mantissa of the second number, the third input and the fourth input of the first conditional selection unit of the lower part of the mantis are connected respectively to the third input and the fourth input of the second conditional choice unit of the older part of the mantissa, the third input and the fourth input of the first conditional choice unit of the younger part of the mantissa are connected respectively to the first input and to the second input the maximum selection block of the exponential part of the two operands, and the third input and the fourth input of the first conditional selection block of the lower part of the mantissas are connected respectively to the first input and to the second the input block difference exponent, The first output of the first conditional selection block of the lower part of the mantis is connected to the first inputs of the first block and the second formation unit of the saturation value, the second output of the first conditional choice block of the lower part of the mantissa is connected to the first input of the mantissa shift block, the first output of the second conditional selection block of the older part of the mantissa is connected with the second input of the first block forming the saturation value and with the second input of the second block forming the saturation value, the second output of the second conditional selection block is old the neck of the mantissa is connected to the second input of the shift unit of the mantissa, the output of the maximum selection block of the exponential part of the two operands is connected to the input of the unit addition unit and the first input of the third conditional transition unit, the output of the unit addition unit is connected to the second input of the third conditional transition unit, the output of the difference unit of the exponents is connected to the input of the absolute difference unit, the output of which connected to the third input of the mantissa shift unit, the first output of the mantissa shift unit is connected to the third inputs of the first and second saturation units, the second output of the bl Single shear mantissa is connected to fourth inputs of the first and second blocks forming saturation value, the first output of the first block of forming the saturation value is connected to the first input of the block of forming the inverse code and the first input of the second block of conditional transition; the second output of the first block of forming the saturation value is connected to the second input of the block of forming the inverse code, with the first and third inputs of the first block of the conditional transition , with the third input of the second conditional transfer unit and with the third input of the third conditional transfer unit, the output of the second formation unit of the saturation value is connected to the fourth input mi of the first conditional transfer unit, the second conditional transfer unit and the third conditional transfer unit, and The first and second outputs of the inverse code generation unit are respectively connected to the first and second inputs of the double format subtraction unit, the first output of which is connected to the second input of the second conditional transfer unit, and the second output to the second input of the first conditional transfer unit, outputs of the first, second and third conditional transition blocks serve as exits — the mantissa of the higher digits, the mantissa of the lower digits, and the exponent of addition / subtraction of numbers.

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