SU251959A1 - DEVICE FOR AUTOMATIC INSPECTION OF CORNER CONVERTERS - CODE - Google Patents

Description

According to the main author. St. No. 225579, a device is known for automatically checking angle-to-transducers containing p parallel-connected transducers associated with a drive, a pulse generator connected to a distributor, an amplifier, triggers, logic and threshold circuits. Two threshold circuits connected to logic circuits are connected to each output of the converters, the outputs of the logic circuits of each pair of neighboring converters are connected to a mismatch circuit. The outputs of the mismatch circuits are connected to the single inputs of the buffer triggers, the zero inputs of which are connected to the first bit of the distributor. The latter is also connected to one of the inputs of the "I" circuit and to the first bit of one of the converters, the other input of the "I" circuit is connected to the first output of the selected converter; the output of the circuit “AND is connected to the additional inputs of the threshold circuits, and the buffer triggers are connected to the pulse counters.

These devices do not exclude errors associated with distributor faults.

The proposed device is characterized in that it comprises a frequency divider, a driver, valves, and a coincidence circuit, with the pulse inputs of the valves connected to the outputs of the buffer triggers, potential

gate inputs are connected to a driver connected via a coincidence circuit with the last bit of the distributor and the output of a frequency divider connected to the generator

pulses, and the outputs of the valves are connected to the inputs of the counters.

This increases the noise immunity and reliability of the device. The drawing shows a block diagram of the proposed device.

On Kaledy discharge converters L 2, 3, planted on the shaft of the engine 4, successively interrogating pulses from the common distributor 5.

The number of outputs of the distributor is k +, where k is the converter size. An extra (k + 1) -th clock cycle is required to prepare logic circuits for the next cycle.

survey. The pulse propagation in the distributor is carried out by the generator 6. The threshold circuits 7-18 operate every time when the output voltage of the corresponding converter exceeds a single level. Signals that have passed through threshold circuits are analyzed by logic circuits 19-24, whose purpose is to convert a V code to a binary code.

A mismatch scheme 25, 26, 27 (e.g., scheme 25 is associated with schemes 19 and 24.

It is assumed that the mismatch of the output signals of any pair of logic circuits at a given time is a failure. All converters operate synchronously, with the same initial setting, so the signal at the output of the mismatch circuit indicates the presence of a fault in one of the two converters.

The correct operation of the mismatch circuits requires the complete identity of the code combinations at the output of the logic circuits, for which it is necessary to eliminate the ambiguity of reading the first bit of any converter with respect to the others (the ambiguity of the remaining bits is eliminated by the logic circuit). Otherwise, the code combinations of the transducers may differ by one low-order bit.

For this purpose, the distributor polls the pen discharge of only one (first) of the tested converters. In this case, the output signal A of the selected converter is taken as the output signals corresponding to the first bits of the other converters. This signal goes to the additional inputs of the threshold circuits.

Since the converter code is read sequentially, it is necessary that the connection between the output A of the first converter and the inputs of the threshold circuits be made only on the first clock cycle of the distributor. For this, the device includes an “AND 25” circuit. At its one input, a clock pulse from the first bit of the distributor arrives, at the second input — 7 output signals A of the first converter. Circuit 28 only works if IF; the result of reading the first digit corresponds to "1. Signals from other bits cannot trigger triggers. The output of the & 28 circuit is associated with threshold circuits connected to the outputs A.

Since, when converting a V code to a binary code, a failure in one of the transducer bits may cause failures in other bits, it is practically impossible to distinguish independent failures (i.e., in different bits of the converter, independently of one another) and dependent faults (caused by faults in previous bits). Therefore, any number of failures of each pair of transducers marked in one cycle of the detector is recorded as one failure of this pair.

The failures for one polling cycle are fixed by buffer triggers 29, 30, 31. The failures of each pair of converters are fixed for a long time by & chipper 32, 33,: 34.- Triggers 35, 36, 37 indicate that the counters overflow .

The buffer triggers 29, 30, 31 are polled once per distributor operation cycle when polling the first bit (i.e., at the 1st cycle).

Since, according to the first operation clock of the distributor, a common signal arrives at all threshold circuits (from the AND 28 circuit, the mismatch schemes at the first clock step do not work. Therefore, the polling of buffer triggers is performed unobstructedly.

Valves 38, 39, 40, driver 41, coincidence circuit 42 and frequency divider 43 are designed to eliminate the effect of faults in the distributor 5 on the information about the inverters' faults. The conversion factor of the frequency divider 43 is equal to k + 1 (the number of outputs of the distributor 5). Thus, with proper operation, the frequency divider 43 and the distributor 5 at the end of each polling cycle on

(k + 1) -th pulse through a coincidence circuit

42 and the driver 41 will pass a signal to the valves 38, 39 40. This will allow the transfer of information from the buffer triggers to the counters. Output pulse duration

the driver 41 must correspond to the inequality - where the f-frequency of the generator 6. If the distributor 5 fails (or the frequency divider 43, the pulses will come to the circuit 42 at different times, the enabling signal will not come to the valves 38, 39, 40.

It is obvious that a simultaneous (in the same cycle on the same survey cycle) failure of the distributor 5 and the frequency divider

43 slightly ten. Therefore, errors caused by distributor failures will not be recorded in the counters.

The threshold and logic circuits are duplicated in such a way that the faults of each converter are recorded in two adjacent counters. Obviously, such a construction of the circuit makes it possible to exclude failures of the device itself from the total amount of failures and, in addition, to determine the number of the failed converter.

Subject invention

Device for automatic verification of angle converters - auth. St.

No. 225579, characterized in that, in order to increase the noise immunity and reliability of the device, it comprises a frequency divider, a driver, valves and a coincidence circuit, with the pulse inputs of the valves connected

with the outputs of the buffer triggers, the potential inputs of the valves are connected to the driver connected via the coincidence circuit with the last distributor bit and the output of the frequency divider connected to the pulse generator, and the outputs of the valves are connected to the inputs of the counters.

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