SU1805793A1 - Method for producing bipolar integrated-circuit structures - Google Patents

Method for producing bipolar integrated-circuit structures

Info

Publication number
SU1805793A1
SU1805793A1 SU4851433/25A SU4851433A SU1805793A1 SU 1805793 A1 SU1805793 A1 SU 1805793A1 SU 4851433/25 A SU4851433/25 A SU 4851433/25A SU 4851433 A SU4851433 A SU 4851433A SU 1805793 A1 SU1805793 A1 SU 1805793A1
Authority
SU
USSR - Soviet Union
Prior art keywords
regions
silicon
deposition
formation
circuit structures
Prior art date
Application number
SU4851433/25A
Other languages
Russian (ru)
Inventor
Д.М. Боднарь
С.Н. Корольков
К.Г. Толубаев
Original Assignee
Научно-исследовательский институт электронной техники
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Научно-исследовательский институт электронной техники filed Critical Научно-исследовательский институт электронной техники
Priority to SU4851433/25A priority Critical patent/SU1805793A1/en
Application granted granted Critical
Publication of SU1805793A1 publication Critical patent/SU1805793A1/en

Links

Abstract

FIELD: microelectronics, integrated circuit manufacturing process. SUBSTANCE: method involves production of buried layers in silicon substrate, deposition of epitaxial layer, formation of emitter, base, and collector regions in it, opening of contact windows in insulating coat, deposition of metal layer and its photolithographic treatment. Novelty in this method is that before depositing metal layer structures are subjected to plasma-chemical or reaction-ion etching involving complete removal of insulating layer and 30-80 nm of silicon from regions of formation of contact windows during selective etching of silicon in p-type regions to sinicon in n-regions at interval of 1.5: 1-2.5: 1. EFFECT: improved parameters of bipolar integrated-circuit structures. 3 cl
SU4851433/25A 1990-07-16 1990-07-16 Method for producing bipolar integrated-circuit structures SU1805793A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SU4851433/25A SU1805793A1 (en) 1990-07-16 1990-07-16 Method for producing bipolar integrated-circuit structures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU4851433/25A SU1805793A1 (en) 1990-07-16 1990-07-16 Method for producing bipolar integrated-circuit structures

Publications (1)

Publication Number Publication Date
SU1805793A1 true SU1805793A1 (en) 1996-04-27

Family

ID=60536938

Family Applications (1)

Application Number Title Priority Date Filing Date
SU4851433/25A SU1805793A1 (en) 1990-07-16 1990-07-16 Method for producing bipolar integrated-circuit structures

Country Status (1)

Country Link
SU (1) SU1805793A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2653843C2 (en) * 2016-08-01 2018-05-15 Акционерное общество "Научно-производственное предприятие "Алмаз" (АО "НПП "Алмаз") Method of increasing the density and stability of a matrix current of a multiple auto-emission cathode
RU195547U1 (en) * 2019-11-13 2020-01-31 Акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" PLANAR SILICON P-N-P TRANSISTOR

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2653843C2 (en) * 2016-08-01 2018-05-15 Акционерное общество "Научно-производственное предприятие "Алмаз" (АО "НПП "Алмаз") Method of increasing the density and stability of a matrix current of a multiple auto-emission cathode
RU195547U1 (en) * 2019-11-13 2020-01-31 Акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" PLANAR SILICON P-N-P TRANSISTOR

Similar Documents

Publication Publication Date Title
US4016007A (en) Method for fabricating a silicon device utilizing ion-implantation and selective oxidation
EP0076106B1 (en) Method for producing a bipolar transistor
DE3681785D1 (en) METHOD FOR PRODUCING SELF-ADJUSTED BIPOLAR TRANSISTOR STRUCTURES WITH A REDUCED BASE RESISTOR.
EP0231811B1 (en) Method for manufacturing integrated electronic devices, in particular high voltage P-channel MOS transistors
SU1805793A1 (en) Method for producing bipolar integrated-circuit structures
JPS6252950B2 (en)
JPH09306865A (en) Manufacturing semiconductor device
KR970703615A (en) METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH BiCMOS CIRCUIT
JPS5764927A (en) Manufacture of semiconductor device
JPS6161268B2 (en)
SU1702826A1 (en) Process of manufacture of transistor structures with dielectric insulation
JPS5922381B2 (en) Handout Taisoshino Seizouhouhou
JPS6249643A (en) Semiconductor device and its manufacture
JPS588143B2 (en) How to use warm air
RU96106994A (en) METHOD FOR PRODUCING BIPOLAR PLANAR N-P-N TRANSISTORS
JPH0479328A (en) Production of semiconductor device
JPS5583230A (en) Producing semiconductor device
SU1538830A1 (en) Method for producing bipolar-transistor integrated circuits
JPS5957421A (en) Manufacture of semiconductor device
WO1999025003A3 (en) Manufacture of a semiconductor device with a poly-emitter bipolar transistor
FR2449332A1 (en) METHOD OF PROTECTING CONTACT AREAS ON SEMICONDUCTOR DEVICES
JPS59144148A (en) Manufacture of semiconductor device
JPS5599777A (en) Manufacture of semiconductor device
JPS63197331A (en) Production of semiconductor device
JPS594163A (en) Manufacture of semiconductor device