SU1756885A1 - Divider - Google Patents

Abstract

The invention relates to computing and can be used in high-speed arithmetic devices for performing the operation of dividing numbers. The aim of the invention is to improve the speed of the device. The device contains registers 1, 2 divisible and divisor, adder 3 quotient, unit 4 dividing the truncated numbers, unit 5 multiplication, two subtractors 6, 7, switch 8 and unit 9 controls. 1 hp f-ly, 4 il.v

Description

binational adder, fourth input 5 inverse outputs of the O-flip-flop.

Fiz.Z

W / 6

with

/.r

7x 1

 h and "jf

y / jo

% - /:

IwjWSj / to l

r g w i

#

Claims (3)

Claim . . one . A device for dividing, containing registers of divisible and divisor, adder of quotient, block of division of truncated numbers, multiplication unit, two subtractors and control unit; the device data input is connected to the information input of the register of the divider and the first information input of the switch, the output of which is connected to the information input of the register of the dividend, whose output connected to the input of the decremented first subtractor, the inputs of the subtracted and borrowing of which are connected to the outputs of the first and second groups of the multiplication unit, respectively, the first information input of the unit It is connected to the output of the register of the divider, the output of the most significant digits of which is connected to the input of the divider of the division block of truncated numbers, the input of the dividend of which is connected to the output of the higher digits of the register of the dividend, and the output of the division block of the truncated numbers multiplications, difference outputs and borrowings of the first subtractor are connected to the inputs of the second subtractor, respectively, reduced and subtracted, the output of which is connected to the second information the input of the switch, the device's synchronization input is connected to the synchronous inputs of the registers of the dividend and divisor of the adder, the private and the control unit, the first output of which is connected to the first control input of the switch and the installation input to the O * of the private adder, the output of which is connected to the output of the private device, the second output the control unit is connected to the second level control input of the switch a, the third output of the control unit is connected to the write enable input of the register of the Divisible, the fourth output of the control unit is connected to the input of Matrix register entries, the fifth output of the control unit is connected to the output of the sign the end of the division of the device, about tl and ch thu e e with the fact that, in order to increase the device speed, the output of the younger 5 bits of the second subtracter is connected to the third information input of the switch, the output of the two most significant bits of the second subtracter is connected to the control unit, the second And the third inputs Ϊ0 which is connected to the inputs of the first and second constants of the device, respectively, the fourth input of the control unit is connected to the input of the bit depth of the private device, the third output of the control unit 15 is connected to the input of the recording resolution of the private adder; the sixth output of the control unit is connected to the third control input of the switch; the seventh and eighth outputs of the control unit are connected to the first 20 and the second inputs of the shift value of the adder private. 2. The device according to claim 1. On the basis of the fact that the control unit contains a counter, a microinstruction memory node, two elements 14, 14, the elements OR and NOT, the O-trigger. the comparison circuit, a register, two combinational adders and a switch, while the synchronization input of the block is connected to the counting input of the counter and the synchronization inputs 30 of the O-flip-flop and a register, the reset input of which is connected to the input of the element NOT. with the first outputs of the block and memory of microinstructions, the second output of which is connected to the register write enable input and 35 the third output of the block, the second output of which is connected to the output of the first element And and the first control input of the switch, the second control input which is connected to the output of the second element And 40 is the sixth output of the block; the output of the counter is connected to the address input of the memory node mi- rokomand, the third output of which is connected to the fourth output of the block, the first input of which is connected to the first and second inputs of the OR element, the direct output of which is connected to the information input of the O-flip-flop and the first input of the first element AND, the second input of which is connected to the output of the element NOT and the first input of the second And element, the second input of which is connected to the inverse output of the OR element, - the second and third inputs of the block are connected to the first information inputs of the first and second combination totalizers, respectively, the outputs of which are sums. connected to the first and second information. with the corresponding inputs of the switch, the output of which is connected to the information input of the register, the output of which is connected to the first input of the circuit 17 1756885 18 comparison and the second information input of the first combinational adder, the output of the transfer of which is connected to the second information input of the second combinational adder, the fourth input unit is connected to the second input of the comparison circuit, the output of which is connected to the fifth output of the unit, the seventh and eighth outputs of which are connected to the direct and 5 inverse outputs of the O-flip-flop. Figz 1756885 S- ^ p-Ts yy V> / ^ ι * And · PIIII - I)