GB1388593A - Output format control for electronic computers - Google Patents
Output format control for electronic computersInfo
- Publication number
- GB1388593A GB1388593A GB1822472A GB1822472A GB1388593A GB 1388593 A GB1388593 A GB 1388593A GB 1822472 A GB1822472 A GB 1822472A GB 1822472 A GB1822472 A GB 1822472A GB 1388593 A GB1388593 A GB 1388593A
- Authority
- GB
- United Kingdom
- Prior art keywords
- register
- digits
- registers
- shift
- contents
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K13/00—Conveying record carriers from one station to another, e.g. from stack to punching mechanism
- G06K13/02—Conveying record carriers from one station to another, e.g. from stack to punching mechanism the record carrier having longitudinal dimension comparable with transverse dimension, e.g. punched card
- G06K13/06—Guiding cards; Checking correct operation of card-conveying mechanisms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/02—Digital computers in general; Data processing equipment in general manually operated with input through keyboard and computation using a built-in program, e.g. pocket calculators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
- G06K7/08—Methods or arrangements for sensing record carriers, e.g. for reading patterns by means detecting the change of an electrostatic or magnetic field, e.g. by detecting change of capacitance between electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Artificial Intelligence (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Computer Vision & Pattern Recognition (AREA)
- Human Computer Interaction (AREA)
- Complex Calculations (AREA)
- Calculators And Similar Devices (AREA)
- Input From Keyboards Or The Like (AREA)
- Shift Register Type Memory (AREA)
- Time Recorders, Dirve Recorders, Access Control (AREA)
Abstract
1388593 Digital calculator ING COLIVETTI & C SpA 19 April 1972 [22 April 1971] 18224/72 Headings G4A and G4H A digital calculator includes a recirculating memory comprising two registers containing a series of digits and symbols respectively and is arranged serially to read the digits from the first register with the symbols from the second register interposed in the series of digits in appropriate positions. The calculator is similar to that described in Specification 1,259,210 which is referred to, but includes two one character (eight bit) shift registers KA, KB. Specification 1,103,384 is also referred to. General.-The calculator includes a delay line store LDR containing sixteen registers each storing thirty-one eight-bit characters, the registers being interleaved at bit level. Corresponding bits from all registers are available simultaneously at the output of serial/parallel converter 19. A read only memory contains program sub-routines accessed by "jump" instructions, (see Specification 1,259,210). Two single character shift registers KA and KB may be interposed in the circulation path of a selected delay line register so as to shift that register relative to the others. The shift registers may be connected to adders 34, 35 to function as counters, see "Arithmetic operations in Digital Computers"-Richards p. 198. Output to peripheral.-Data from one of the delay line registers may be transferred to a peripheral, e.g. a printer, with punctuation symbols inserted between selected digits. Numeric data is loaded in register A (output LA from converter 19) and the symbols in the appropriate character locations of register M (output LM). Switching network 97 connects shift register KA in the circulation loop of register M for a number of delay line cycles until the contents of registers A and M are aligned. Register A is then connected to shift register KB which functions as an output buffer. The digits in register A are read out serially until a symbol is detected in the M register at the character position corresponding to that in the A register which is about to be read out. The symbol is read from register M via KB and the serial read out from register A resumed. Fixed length data.-Arrangements are provided for limiting to 15 the number of digits used in calculations by discarding digits of lesser significance. During a circulation of register A the number of digits is counted by shift register KA, in conjunction with adder 34, in increasing order of significance starting with the least significant digit, the contents of the counter having been preset to 15. The digits read from the register are prevented from recirculating until the counter, which has a maximum count equal to the number of digit positions in the register, i.e. 31, overflows. Subsequent digits are then recirculated so that the number of digits in register A at the end of the cycle is 15. Fixed/floating point conversions.-Initially register A contains a fixed point number and register M a single zero digit which contains a decimal point. The decimal points in the registers are aligned by relative shifting (see above) and a bi-stable (N7) is set to 1 by the decimal point in register A and reset to zero by a non-zero digit following the point so as to indicate whether the contents of register A are greater than or less than one. If the contents are less than one register A is connected to shift register KA so as to be shifted one place left during each cycle, adder 34 subtracting one from the (initially zero) contents of register M. The process continues until the decimal point in register M is aligned with the most significant non-zero digit in register A. The relative shifting is then halted and a decimal point written in register A aligned with that in register M. Register A thus contains the mantissa and register M the exponent. If the contents of register A are greater than one the procedure is similar except that register M is circulated via shift register KB and adder 35 adds one into register M for each cycle. The floating point representation may be written in a single register as a fixed point number whose integral part represents the mantissa. Reverse conversions from floating point (represented as a fixed point number, see above), to fixed point are described. The single number is separated into integral and decimal portions stored in registers M and A respectively. The sign of the exponent is tested and if negative causes register A to be recirculated via shift register KB, adder 35 adding one into register M at each cycle until the contents of M are zero when the decimal point in register A is erased and rewritten aligned with that in register M. If the exponent sign is positive the procedure is similar except that register A is recirculated via shift register KA, adder 34 subtracting one from register M at each cycle.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT6833671 | 1971-04-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1388593A true GB1388593A (en) | 1975-03-26 |
Family
ID=11309023
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB5939172*A Expired GB1388595A (en) | 1971-04-22 | 1972-04-19 | Separation of exponent from mantissa preparatory to the conversion from floating point to fixed point |
GB1822472A Expired GB1388593A (en) | 1971-04-22 | 1972-04-19 | Output format control for electronic computers |
GB5939272*A Expired GB1388596A (en) | 1971-04-22 | 1972-04-19 | Conversion from fixed to floating point in electronic computers |
GB5939072*A Expired GB1388594A (en) | 1971-04-22 | 1972-04-19 | Digit limitation in a digital electronic computer |
GB5939372*A Expired GB1388597A (en) | 1971-04-22 | 1972-04-19 | Read write structure for programme cards |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB5939172*A Expired GB1388595A (en) | 1971-04-22 | 1972-04-19 | Separation of exponent from mantissa preparatory to the conversion from floating point to fixed point |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB5939272*A Expired GB1388596A (en) | 1971-04-22 | 1972-04-19 | Conversion from fixed to floating point in electronic computers |
GB5939072*A Expired GB1388594A (en) | 1971-04-22 | 1972-04-19 | Digit limitation in a digital electronic computer |
GB5939372*A Expired GB1388597A (en) | 1971-04-22 | 1972-04-19 | Read write structure for programme cards |
Country Status (6)
Country | Link |
---|---|
CA (1) | CA978653A (en) |
CH (1) | CH550438A (en) |
DE (1) | DE2220329C3 (en) |
FR (1) | FR2136620A5 (en) |
GB (5) | GB1388595A (en) |
SU (1) | SU568398A3 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4036430A (en) * | 1976-05-13 | 1977-07-19 | Ebco Industries, Ltd. | Manually operable card reader |
GB2142176A (en) * | 1983-06-24 | 1985-01-09 | Hawker Siddeley Revenue Contr | Read and erase device |
GB2241810A (en) * | 1990-03-09 | 1991-09-11 | Mars Inc | Data card reader |
US5619198A (en) * | 1994-12-29 | 1997-04-08 | Tektronix, Inc. | Number format conversion apparatus for signal processing |
US6263426B1 (en) | 1998-04-30 | 2001-07-17 | Intel Corporation | Conversion from packed floating point data to packed 8-bit integer data in different architectural registers |
US6266769B1 (en) | 1998-04-30 | 2001-07-24 | Intel Corporation | Conversion between packed floating point data and packed 32-bit integer data in different architectural registers |
DE10056047C1 (en) * | 2000-11-11 | 2002-04-18 | Bosch Gmbh Robert | Automatic conversion of arithmetic term from floating to fixed point arithmetic involves combining operand, result normalizing factors into constants until number of constants minimized |
-
1972
- 1972-04-19 GB GB5939172*A patent/GB1388595A/en not_active Expired
- 1972-04-19 GB GB1822472A patent/GB1388593A/en not_active Expired
- 1972-04-19 GB GB5939272*A patent/GB1388596A/en not_active Expired
- 1972-04-19 GB GB5939072*A patent/GB1388594A/en not_active Expired
- 1972-04-19 GB GB5939372*A patent/GB1388597A/en not_active Expired
- 1972-04-21 CH CH597872A patent/CH550438A/en not_active IP Right Cessation
- 1972-04-21 SU SU7201782279A patent/SU568398A3/en active
- 1972-04-21 DE DE2220329A patent/DE2220329C3/en not_active Expired
- 1972-04-21 FR FR7214312A patent/FR2136620A5/fr not_active Expired
- 1972-04-24 CA CA140,363A patent/CA978653A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR2136620A5 (en) | 1972-12-22 |
CH550438A (en) | 1974-06-14 |
DE2220329A1 (en) | 1972-10-26 |
DE2220329C3 (en) | 1982-02-11 |
GB1388597A (en) | 1975-03-26 |
DE2220329B2 (en) | 1981-06-11 |
GB1388594A (en) | 1975-03-26 |
CA978653A (en) | 1975-11-25 |
GB1388596A (en) | 1975-03-26 |
GB1388595A (en) | 1975-03-26 |
SU568398A3 (en) | 1977-08-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |