SU1753491A1 - Memory device - Google Patents

Abstract

The invention relates to memory devices, in particular to semi-permanent memory with error correction. The aim of the invention is to increase the reliability due to the correcting ability of the device. The goal is achieved by introducing an additional accumulator of check bits of the Hamming codes, additional correction blocks, switches that form a matrix. The invention consists in using an orthogonal matrix coding with storage elements by using Hamming code words separately for each row and for each column of the matrix and using a Commutator, transmitting the rows of the matrix, corrected by the nodes of the rows or columns of the matrix. 2 tab., 5 Il.

Description

The invention relates to memory devices (RAM), in particular to semi-permanent memory with error correction.

Known memory with the correction (correction) of single and the detection of double errors in codewords using Hamming code.

The disadvantage of such devices is the impossibility of correcting more complex errors.

It is also known a storage device capable of correcting more complex errors, including a double error in one of the rows or in one of the columns of the matrix formed by the storage elements of the accumulator. More complex errors (for example, two double errors in different rows of the storage matrix) are not corrected by this device.

The aim of the invention is to increase the reliability of the device by increasing its correction ability.

The goal is achieved by increasing information redundancy by introducing an additional accumulator of control bits of the Hamming codes, additional correction blocks and a matrix of output switches, through which the output signals of the main or additional correction blocks are passed to the device output depending on where and how the defective bits are located .

Figure 1 shows the schematic of the claimed device; 2 and 3, the error places in the accumulators of the device (the error places are indicated by x); figure 4 is a diagram of the nodes of the syndrome and decoders; figure 5 - scheme of nodes correction.

The memory (figure 1) contains an information storage device 3 containing mxn information

WITH

and

WITH

 about

of the main bits of the 4 control bits of the 2 Hamming codes, the additional drive of the 10 additional check bits of the 9 Hemmba codes, the main correction blocks 5, the additional correction blocks 11, and the matrix of switches 12 containing n rows and m columns.

To explain the operation of the device, it will introduce the concepts of: single errors, double horizontal, double vertical, triple horizontal and vertical errors (Fig. 2). In FIG. 2a, there are 5 single errors; in FIG. 26 - one single and one vertical double errors; in FIG. 20, one is double horizontal and one is single error; in fig. 2d - one triple vertical and one single error; fig 2d - triple horizontal error; Fig 2E - two double errors - horizontal and vertical, located angle.

The device works as follows.

In the absence of errors, as well as in the presence of only single errors, the information outputs of the 13 main correction blocks 5 are formed by nxm (in Fig. 1, 8 bytes of 8 bits) of the corrected information signals, since each of the main correction blocks 5, at the inputs of which There is a single error, correct it. For the same reason, at the information outputs 14 of the additional correction blocks 11, nxm of the same corrected output signals are also formed (i.e., the signals 13 and 15 coincide).

The control inputs 15 of the switches 12, related to a specific row of drives 3 and 4 and, respectively, to a certain main correction unit 5, are connected to the double error output 16 of this main correction unit 5. Therefore, in the absence of a double error in this row of drives 3 and 4, the outputs 17 of the switches 12 of this construction will pass the output signals of this main correction unit 5.

At the outputs (Fig. 2b) of that additional correction block 11, at the inputs of which there is a double (vertical) error, this error will not be corrected (since the normal Hamming move only detects, but does not correct such errors). However, at outputs 17 of all mn switches 12, the correct nm-hpc code is generated, since the output signals of the main correction blocks 5 will pass through these switches (none of these correction blocks on their m + k information inputs have double errors). A similar picture will take place in the case shown in FIG. 2d (despite the triple vertical error),

In the case shown in FIG. 2c (one

a single error in the 7th byte and one horizontal double in the 4th byte); a single error will be corrected as in the previous cases (Fig. 2a, b, d). What concerns

double horizontal error, it will also be corrected, since at the output 16 of the main correction unit of the 4th byte, a double error signal is generated that switches the switches 12

4th byte and all the output signals of the main correction unit 5 will pass through these switches (as in all other nm-m switches 12), and the output signals of 14 additional correction blocks 11 refer to the 4th byte (i.e. one signal of the 4th bit from all eight additional correction blocks 11).

In the cases shown in FIG. 2d and e, error correction will not occur, i.e. the device will not work correctly (in addition, in case of a triple horizontal error, error detection will not occur, and the fourth error will add a fourth error produced by the main unit

correction byte, in which there was a triple error, which the main correction unit will take for a single). In the case shown in FIG. 2e, two errors at the outputs of the device 17 will be corrected (the lower error is the main correction unit, and the right error is an additional correction unit), and a third error, located at the top of the corner, will remain uncorrected, since

located at the intersection of two double faults - horizontal and vertical. Despite the noted deficiency, the proposed device has a high corrective ability and can

correct various and very complex mistakes. Such a case of a complex but fully adjustable situation is shown in FIG. 3 for example.

4 shows one of the possible

diagrams of nodes 6 of the syndrome and decoders 7 main correction blocks 5 for cases m - 8, 5. The syndrome node contains four IS modulo two (convolutions) C1-C4, producing 4 bits of the syndrome in

5 in accordance with Table 1 of the classic Hamming code.

At the inputs of each of the convolutions 18, there is only one check bit K, which, with a healthy device, complements

parity sum modulo two remaining input signals of this convolution.

The fifth check bit KB adds to parity the sum of all 12 Hamming stroke bits (P1-P7, K1-K4), so the output signal of convolution 19 is O (and the output signal of inverter 27 is 1), if at 13-bit In the code (P1-P7, K1-K5) there are no errors or there is even an error. The output signal of the element OR 28 in the absence of errors in a 12-bit code is equal to O (since all output signals of convolutions of 18 are equal to O) and equal to 1 if there is any error in the 12-bit code (since one or more output convolution signals 18 rayons 1).

Thus, with an even error (including the most likely of them, a double error), both output signals of the And 29 element are equal to 1 and therefore, at the output of this element, the output signal 16 of the double error will be equal to 1. Thus, a double (even ) error node 6 syndrome.

The decoder 7 consists of four inverters26. the inverting output signals of convolutions of 18, eight (according to the number of bits P1-P8) 4-input (according to the number of code columns in Table 1) elements AND 20. The output of each of the elements 20 produces an error signal of the corresponding information bit P, since 4 inputs 21 kzd- GDG elements 20 are connected to the outputs of the convolutions 18 and inverters 26 in accordance with table 1. For example, the inputs of the element 20, which generates an error signal of the RB discharge, are connected to the outputs of convolutions C2 and NW and the outputs of two inverters 26, which invert the output signals of convolutions C1 and C4. Such a connection is defined by line P6 in Table 1 (code 0110). Therefore, if an error occurs in discharge P6, then at the outputs of convolutions 18 a syndrome code 0110 is formed, shown in Table 2 (in the absence of errors, i.e. if the number of units is even at the inputs of each of convolutions 18, the output signals of all 4 convolutions 18 are equal to zero). Therefore, all 4 input signals of element 20 of bit P6 will be equal to 1 and at output 22 of this element a signal 1 will be generated, signaling an error in bit P6.

Similarly, nodes of syndrome 6 and decoders 7 additional correction blocks 11 are constructed. Figure 5 shows one of the possible schemes of the node 8 correction of the main blocks of the 5 correction. The circuit contains eight two-input adders 22 modulo two, eight 2-input elements AND 24, and one inverter 25. The task performed by correction unit 8 is (assuming no double error, inverting that output information signal Pi of information storage 3, which has an error (i.e., a ti bit Pi. for which there is a corresponding signal 22 rcP), at the output of the decoder 7 of the main correction unit 5.

In this case, there are two signals 1 on both inputs of the corresponding element 24 (one of them comes from the output of the inverter 25 in the absence of a double error, and the second - the signal 22 of the CSR | from the corresponding output of the decoder 7). The output signal of the AND 24 is applied to one of the inputs of the corresponding adder 23 modulo two, which invert the corresponding information signal PI of the information storage device 3.

Similarly, the nodes 8 correction additional blocks of the correction 11.

Claims (1)

Invention Formula A storage device containing the information storage, the main storage of the check bits of the Hamming codes, the main correction blocks, the first inputs of each of which are connected to the corresponding outputs of the information storage, and the second inputs of each of the main correction blocks are connected to the corresponding outputs of the main storage of control code digits Hamming, characterized in that, in order to increase the reliability of the device, it contains an additional accumulator of check bits of the Hamming codes , commutators that form the matrix, additional correction blocks, the first inputs of each of which are connected to the corresponding outputs of the information storage device, and the second inputs of each of the additional correction blocks are connected to the corresponding outputs of the additional accumulator of control bits of the Hamming codes, the information outputs of each of the additional correction blocks are connected with the first information inputs of the switches of the corresponding matrix column, the second information inputs of the switches are each The matrix rows are connected to the information outputs of the corresponding main correction unit, the double error detection output of each main correction block is connected to the control inputs of the matrix, the outputs of the matrix switchers of switches of the corresponding row are matched by the device outputs. Table 1 Table 2 It 5 2 8 FIG. one X x x X l ABOUT) X x at) X X FIG. 2 X x FIG. J L l / U Fuck a j / .fftf sixteen S P I T yJL FIG. five