SU1751766A1 - Majority-redundant memory interface - Google Patents

Abstract

The invention relates to computing and can be used in the construction of highly reliable high-performance redundant computing systems. The aim of the invention is to increase the reliability of the interface by increasing the speed of monitoring emerging failures, adapting the interface to failures and providing dynamic correction of programs. The invention consists in increasing the reliability of the interface by detecting failures not only at the moments of transmitting information through the interface, but also during the conversion of this information in information source blocks. The invention also provides the possibility of dynamically correcting programs recorded in read-only memory. This provides the ability to detect the fact that an approach to the execution of a program section that requires correction, interrupt the operation of the device and go to the execution of the corrected program section, which is stored in the RAM, is returned to the interrupted program. 6 ill., 10 tab. w Ё

Description

The invention relates to computing and can be used in the construction of highly reliable high-performance redundant computing systems.

A major-backup memory interface is known that contains in each channel appropriately interconnected input and output information switches, the first and second internal information switches, a control register, six buffer registers, memory status registers, and input / output devices, the first and the second processor status registers, time and state counters, command and data address counters, the memory unit switchboard, the switches of the first, second and third bits of the processor, three state code switches, address switch, processor tuning switch, overflow signal switches, state counter, time interval counter, counter start block, comparator block, switching control block, code converter, fault decoder, memory block state decoders and processor, first and second reset triggers, first and second processor reorganization control triggers, majority address and control blocks, first and second majority information blocks, ne vy and second elements majority initial setup, the majority of the processor element adjustment, first to fourth AND-ILIVJ

SP

4 o o o

NOT, from the first to the fourth elements of AND-NOT, the first and second elements of OR-NOT, from the first to the eighth elements of AND and from the first to the fifth elements of OR, while the channels are interconnected according to the majority principle.

The disadvantages of this device are the high hardware costs of implementing the interface and the low reliability of the device, since the failure of the equipment organizing reliable data transmission through the interface is equivalent to the failure of the entire interface channel.

The closest to the technical essence and the achieved positive effect to the proposed device is the majority-redundant memory interface containing in each channel the appropriately connected input, output and internal information switches, control register, two buffer registers, valve block, block of majority elements, including three major elements, memory block and I / O device registers, two processor status registers, time interval counters and station, command and data address counters, memory block status switch, first, second and third processor state switches, three state code switches, address switch, processor reconfiguration switch, time counter overflow signals and state counter switches unit, meter start-up unit, comparison unit, control switching unit, code converter, fault decoder, processor and memory block decoders, two reset triggers, two river control triggers Processor configuration, majority control units, addresses and information, two major elements of the initial installation, a major processor reconfiguration control element, four AND-OR-NOT elements, AND-OR element (processor reconfiguration control), four AND-NOT elements, two elements OR - NOT, eight AND elements and five OR elements, while the channels are interconnected according to the majority principle,

The disadvantage of this device is low reliability, due to the fact that the detection of failures (malfunctions) occurs only at the moments of information transmission through the interface. Since processors, as a rule, include a super-memory (general purpose registers), for a certain time

time, they transform the information located in the ultra-fast memory without transferring it through the interface. Failure detection (failure) occurring during

its conversion time by the processor in this interface occurs with a delay of time r, depending on the conversion algorithms. If we take the average time of occurrence of failure (failure) equal to

t, then the ratios of t and t lead to the following consequences.

At t t, the performance of the device decreases due to the loss of operating time, equal to T (T t), if there is

Failure processor fixed in the interface. In this situation, the disadvantage of the device should be called its low performance.

With t g, if there is a failed processor fixed in the interface, or with t 2 tons even with three healthy processors, failures can lead to non-recovery of information by the interface. In this case, the recovery procedure

 information and, accordingly, the computational process can reduce the performance of the device so much that it will lead to the suspension of the computational process, ie, this disadvantage should be classified as low reliability of the device.

Another factor that reduces the reliability of the device is that when connected to it memory blocks in the form of RAM,

having failures in the same-name bits of the same-name addresses in three channels, or in the form of ROMs that have program errors that were not detected during debugging of these programs, or programs that require correction (replacement of ROMs) due to changed operating conditions, such situations in the considered device are classified as a failure of the device as a whole and determine its low reliability under certain conditions of operation of the device,

The purpose of the invention is to increase the reliability of the interface by increasing the efficiency of monitoring emerging failures, adapting the interface to failures and

ensuring dynamic program correction.

Figures 1a-1g are a block diagram of one channel of a majority-redundant memory interface; 2, the connection of the three channels of the device; FIG. 3 shows the execution of the switching control unit of each channel of the device; 4 shows an example of the execution of a meter start block.

The primary backup memory interface (figs, 1a-1d) contains on each channel an input information switch 1, an output information switch 2, a control lock switch 3, a service information switch 4, a control register 5, a first 6 and a second 7 buffer registers, a block 8 gates, majority element block 9, including the first 9.1, second 9.2 and third 9.3 majority elements, interrupt indication control register 10, interrupt indication address register 11, memory block status register 12, I / O device status register 13 a, the first 14 and second 15 processor status registers, a 16 time slot counter, a 17 state counter, a command address address counter 18, a data address counter 19, a memory block state switch 20, a first switch 21, a second 22 and a third bit processor status, first 24, second 25 and third 26 switches of processor codes, address switch 27, processor reconfiguration switch 28, switch 29 for the status counter overflow signals, switch 30 for the time interval counter overflow signals, counter 31 start block, ne A second comparison unit 32, a switching control block 33, a code converter 34, a decoder 35 for failures, a decoder for 36 states of the memory block, a decoder for 37 states of the processor, the first 38 and second 39 triggers of reset, the first 40 and second 41 triggers of control of the processor reconfiguration, majority block 42 address, 43 control and 44 information, the element AND-OR-NOT 45 control control, the first 46 and second 47 major element of the initial installation, the majority element 48 control processor reconfiguration, the first element 49 AND-OR-NOT 49, element AND -OR 5 0 control reconfiguration of the processor, the second 51, the third 52 and the fourth 53 elements AND-OR-NOT, the first 54. the second 55, the third 56 and fourth 57 elements AND-NOT, the first 58 and the second 59 elements OR-NOT, the first 60, the second 61, third 62, fourth 63, fifth 64, sixth 65, seventh 66 and eighth 67 AND elements, first 68, second 69, third 70, fourth 71 and fifth fifth OR elements, second comparison block 73, address comparison block 74 , the decoder 75 signs of interruption, block 76 elements NOT.

In addition, in Figs. 1a-1g, there are: a group 77 of information inputs from a processor, a group 78 of information inputs from an input / output device (HEL), a group 79 of information inputs from memory blocks, a first group 80 of inter-channel outputs of the channel, a first 81 and the second 82 groups of zzhkanalny entrances of the channel, the group 83 information exits of the channel, the first

84.1 and the second 84.2 outputs of the channel interruption request, the first group 85 of control inputs channel a, which includes the first synchronization input 85.1, the first input 85 2 settings, a group of control inputs 85.3, the input switches, the inputs 85.4 and 85 5 of the buffer control registers, internal information switch control input 85.6, inputs, 857 write signals, 85.8 increments and 85.9 decrements of the contents of the command address counter, inputs 85.10 of the write signals and 85.11 increments of the data address counter, input 85.12 of the address switch control, group of inputs 85.13 signs of work of external blocks,

0 the second 85.14 and the third 85.15 synchronization inputs, the second input 85.16 of the installation, the fourth 85.17, the fifth 85.18, the sixth 85.19, the seventh 85 20 and the eighth 85 21 synchronization inputs, the input 85 22 of the decryption control, the ninth 85.23 and the tenth 85 24 synchronization inputs, the first 85.25 and the second 85.26 control control inputs, the second group of 86 control channel inputs, including

0 inputs of the first group 86.1 imitations of zeros and

86.2 unit simulations, the first 86 3 and the second 86 4 channel operation selection inputs, the inputs of the second group 86 5 unit simulations 86.6 ° simulate zeros, the first 87.1 and the second 87.2

5 channel reset inputs, output 88 of the channel comparison results, first 89 and second 90 control inputs of the channel, input 91 of the frequency of the master oscillator, first 92.1 and second 92.2 outputs of the initial channel setting code, first 93.1, second 93.2 and third 93.3 inputs channel comparison code, channel reset output 94, channel timestamp output 95, channel address address group 96, output group 97

5 memory control signals, the third 98 and fourth 99 groups of inter-channel inputs of the channel, the second group of 100 inter-channel outputs of the channel, a group of 101 inputs of control signals of the memory, 5 102 and six hundred 103 groups of inter-channel inputs of the channel, the third group of 104 inter-channel outputs channel, the second inter-channel output 105 of the channel, the third 106 and the fourth 107 inter-channel inputs of the channel, the third inter-channel output 108 of the channel, the fifth 109 and the sixth 110 inter-channel inputs of the channel, the first inter-channel output 111 of the channel, the first 112 and the second 113 inter-channel inputs of the channel first th 114 and second 115 outs

switching control unit, the fourth inter-channel output 116 of the channel, the seventh 117 and the eighth 118 inter-channel inputs of the channel, the fifth inter-channel output 119 of the channel, the ninth 120 and the tenth 121 inter-channel inputs of the channel, the sixth inter-channel output 122 of the channel, the eleventh 123 and the twelfth 124 inter-channel inputs channel, the fourth group of 125 inter-channel outputs of the channel and the seventh group of 126 inter-channel inputs of the channel.

The switching control control unit 33 (FIG. 3) contains the first 127.1, the second 127.2 and the third 127.3 input contacts, connected respectively to the first, second and third inputs of the block 33, and the first 127.4 and the second 127.5 output contacts, connected respectively to the second 115 and the first 114 block 33 outputs.

In this case, in the first channel (FIG. 3), the second input contact 127.2 is connected in pairs with one another with the first output contact 127.4, and the third input contact 127.3 is connected with the second output contact 127.5. In the second channel, the first input contact 127.1 is connected in pairs with the second output contact 127.5, and the third input contact 127.3 is connected with the first output contact 127.4. In the third channel, the first input contact 127.1 is connected to each other in pairs with the first output contact, and the second input contact 127.2 - with the second output contact 127.5,

Block 31 start counters (figure 4) contains the trigger 128 start, the element AND-OR 129 and the element NOT 130. Information input D, the synchronous input C and the input P of the trigger trigger 128 reset are connected to the same inputs 4.85.17 and 71, respectively, of the start block 31 counters, the pulse input 91 of which is connected to the first inputs of the first and second valves of the H-OR 129 element, which by its output forms the output of the block 31. The trigger trigger 128 output is connected to the second input of the first AND-12 12 gate of the element. element NOT 130 is connected to the second input m second gate AND-OR 129.

The control lockout switch 3 is designed to enable the operation of the control, i.e. to allow the transfer of the control results to the information inputs D1-D3 of the control register 5, one by one, depending on the health of the blocks transmitting information through the interface. This is done by the fact that signals from the outputs of the AND elements from the first 60 to the third 62, previously (in the prototype) transmitted directly to the inputs of the first gates of the AND-OR-NOT elements from the second 51 to the fourth 53, are transmitted to them through the first group of inputs of the switch 3

control locks whenever the switches 24-26 of status codes are configured to transmit codes from their inputs from first to

(n + 2) th.

Second, the switch 3 lock

control provides the transfer of the inverse state of signals from the outputs of switches 21-23 of the first to third bits of the processor state to the inputs of the first gates of the second and fourth, respectively

51-53 AND-OR-NOT elements whenever the switches 24-26 of the status codes are configured to transmit signals from the zero potential bus.

Since the processor can work

not only at those times when the processor information is transmitted through the interface, but also at those times when, for example, information is not transmitted through the interface (switches 24-26 are configured

information transfer from the zero potential bus). This allows detecting a failure (failure) in advance and reacting to it accordingly, i.e. increase the speed of control of the device,

Block 76 of the NOT elements is intended to match the levels of the control signals of the AND-OR-HE 51-53 elements and the signals from the outputs of the switches 21-23, since when these signals are transmitted through the first group of information inputs of the switch 3 of the control locks, the signals are also inverted -26 status codes.

The second comparator unit 73 is designed to compare processor information that is indicative of the results of its operation, both during transmission of relevant processor information via the interface, and when the processor information is not transmitted through the interface, but the processor processes the information. With the equality of the compared information, the output of the comparison block 73 is zero, and with the inequality a single signal.

The control control element AND-OR-NE 45 is designed to transmit with inverted control results by comparing the transmitted via the interface

information (signals from the output of the first comparison unit 32) and control results by comparing the processor information independently of its transmission through the interface (signals from the output of the second comparison block 73). Management of the transfer of results

The comparison of the relevant information is produced by the corresponding signals on the first 85.25 and second 85.26 control inputs of the first group of 85 control inputs of the channel. Thus, when comparing information with blocks 32 and 73, the comparison at the output of the AND-OR-HE element is 45 unit, and with the inequality - zero signal level.

The interrupt address address register 11 is for receiving, storing and issuing the address of the memory location, when accessing which is necessary to cause an interruption of the operation of the device

The identification of the address of the memory location during the access to which the interruption should be triggered is performed by the address comparison unit 74 by comparing the contents of the address register 11 of the indication of the interruption with the address of the memory location being accessed.

Since the circulation in the memory is performed in the modes of reading commands and operands, as well as in the mode of recording the results of the corresponding operations, to separate these modes to form a signal of the corresponding interrupt, the interrupt indication control register 10 and the interrupt indication decoder 75 are entered into the device interrupt is intended for receiving, storing and issuing a code of the feature of the memory mode at which an interrupt is to be called, and the decoder 75 identifies this code about the control signals at the input 85.22 of the first group of 85 control signals of the channel.

In principle, for dynamic program correction, it is sufficient to identify only one of the modes (fetching a control word from the memory), but identifying additional read and write data modes expands the functionality of the device, as it can cause interruptions to bypass individual cells, for example, faulty cells. , and simplifies programming in general, i.e. improves the usability of the device.

The device works as follows.

The input information switch 1 transmits information from the internal interface nodes and external devices to the corresponding inputs of the first comparison unit 32, output information switch 2, the majority information block 44 and to the first group of inter-channel outputs of the channel under control

the corresponding codes on group 85.3 of the inputs of the first (group of 85 control inputs of the channel.

Switch 2 output

transmits information from the output of the majority information block 44 (the major information transfer mode) or from the outputs of the switches 1 of the input information of its own and neighboring channels (modes of channel-by-channel information transfer or information transfer of one of the channels in three channels) under control of signals at outputs 114 and 115 switching control unit 33 for information

the inputs of the first 6 and second 7 buffer registers

The switch 4 transmits information (controlled by the signals at the input 85.6 of the first group of 85 controllers)

channel inputs) from the outputs of the first 6 or second 7 buffer registers to the information inputs of the switch 28, the block 31 start counters, registers 10-14 and counters 16 and 17.

The control register 5 stores the control results received at its information inputs Di-D / j, and diagnostic information on the localization of failures (information at the inputs of the De-Dm

register 5) and the state of the monitored equipment until the next failure is detected (signal at the input of register control 5). Synchronization of monitoring results is carried out on

the sync signals at the input 85.1 of the group 85 of the control inputs of the channel up to fixing the failure at least at one of the outputs Qi-Qs of the control register 5, which is ensured by the operation of the AND-NOT element 55 and the element

OR 68,

Setting the register 5 of the control to the initial zero state is performed using the element OR 69 or a signal from the output 85.2 of the group 85 of control inputs

channel, or a signal from the output element OR 72.

The single information on the outputs QI-Qs of register 5 control corresponds to a failure in channels A, B or C or a failure of funds

control in accordance with Table 1 and the presence of a failure already recorded in registers 12-14. The code on the Qe-Qm gains of the register 5 control identifies the equipment in which the detected failure occurred.

 In case of failure in more than one channel, the failed channel is determined by testing, for example, by switching the device to per channel operation.

Buffer registers 6 and 7 are implemented (under the influence of signals at inputs 85.4

and 85.5 group 85 control inputs of the channel) or temporary storage of information (the presence of the mentioned signals) or its omission without storing

The use of two buffer registers improves the performance of the device by parallelizing the transmission of information, while the information from the output of the first buffer register 6 is fed to the information output 83 of the channel and to the information inputs of the address counters 18 commands and 19 data In addition, the information from the outputs of the buffer registers 6 and 7 is fed on the information inputs of the switch 4.

The valve unit 8 generates control signals for the switch 2 output information depending on the signals at the outputs of the switches 24-26 of state codes determining the state of the signals at the outputs of the AND 60-65 elements and the AND-OR-HE49 element.

To transmit channel information through switch 2, output information according to the majority principle at the output of the I-YLI-NE 49 element produces a low signal level providing zero signals at the outputs of the valve block 8 (to the second inputs 86.5 unit imitations and 86.8 imitations of the group of 86 control signals with the exception of the cases described below, single signals are constantly being received). When information is transmitted through switch 2 from one of any channels to the output of the AND-OR-45 element, there is a single signal, therefore the state of the signals at the outputs of the valve block 8 unambiguously corresponds to the state of the signals at the outputs of the And 63-65 elements.

The signals from the outputs of the valve block 8 are transmitted through the majority elements $ .1-9.3 of the block 9 according to the majority principle with the signal inverting. To check the operability of majority elements 9.1-9 3 blocks 9, as well as to generate true information on the outputs of the block 9 majority elements in case of failure of the device reconfiguration not more than two interface channels, signals are used at the second inputs 86.5 unit imitations and 86.6 imitation zeros groups 86 channel control inputs. When generating zero signals at the second input 86.5 of imitation of units in one channel and the second input 86.6 of imitation of zeros in another channel, at the outputs of blocks of 9 major elements in all three channels, the true information of the means of reconfiguration of the third (operational) one was formed, which is ensured by installing single information on the output of the block 8 of the valves of one channel, zero information - the second channel and the true

information - the third (good) channel.

The memory status register 12 is intended to receive, store and output information about the state of the memory blocks,

0 whose information is transmitted via the interface. The state of register 12 is used in the device to control the transfer of information through the interface, as well as to control the monitoring of information transmitted through the interface and the source blocks of this information. Each three-bit area of the register 12 indicates the health state of the corresponding memory block and control. control and reconfiguration of the information transmission path when accessing the corresponding memory block

Table 2 clarifies the assignment of the three-digit code zones of register 12

5 Before starting operation, register 12 is reset by the signal from the output of the element OR 71. The results of the initial setup of the device (to be described below) and the results of testing all the memory blocks are recorded in the memory status register 12, arriving at its information input from the group of 77 channel inputs through the switch 1. majority block 44, switch 2, register 6 and switch 4

5 The air-blast state register 13 operates identically to the three-bit zone of the described register 12. The difference is the initial setting of the register 13, which occurs on the signal from the output of the element OR 72

0 The first register 14 of the processor state identifies the state of the processor, its purpose and operation are identical to the operation of one three-bit zone of register 12 described above. Since the processor is 5 with the main control link, the failures of the three processor channels (code 000 in register 14) are generally results in a system failure as a whole, except when individual bits fail

0 processor output buses. In order to return the device to a working configuration in case of a failure in two processor channels, a second register of 15 states is used, the processor whose operation is performed

5 in conjunction with the processor adjustment switch 28 in two modes - in the information recording mode, when the switch 28 redirects information from the first group of information inputs, or in the ring shift mode, when the switch 28 transmits information from the output to the information input of the register 15 with a shift ( ring) for one bit d

The information recorded in register 15 depends on the information entered in register 14. and is carried out in accordance with Table 3.

The write or shift mode to register 15 is determined by the output state of the major element 48 and, respectively, of the processor reconfiguration control triggers 40 and 41. Since the codes 000, 001. 010 and 100 in register 14 block the control of the processor and, accordingly, the possibility of switching on the flip-flops 41 and 40, in this case, switching the operation of the register 15 to the ring shift mode and controlling the operation of the interface from the register 15 is excluded.

The first (second) register 14 (15) of the processor states is reset by a signal from the output of the element 71 (72) OR.

The 16 time interval counter forms time stamps that determine the device testing time for each configuration, those being the frequency divider for the frequency signals of the master oscillator, which arrive at the counter input from the channel input 91 through the meter start block 31

Setting the counter 16 to the initial zero state is performed by the signal from the output of the element OR 71 Since the counter 16 is also used as part of the watchdog timer (to be described later), it is provided for recording information (the counter recalculation code) supplied to its information input from one of the sources of the switch 1 and the synchronized signal at the input 85 of the channel.

The signals from the overflow output of the counter 16 are transmitted through the switch 30 to the estimated input of the counter 17 of the states through the element OR-NOT 59 and the majority element 46 to the input of the element OR 72 to generate reset signals if there is no signal at the input 89 of the channel

The state counter 17 generates processor and memory block reconfiguration codes identified by the first three-bit zone of register 12 when selecting a serviceable configuration of blocks when the interface is put into operation. At initial setting of a serviceable configuration of blocks, the lower two bits of the counter 17 state determine the choice of serviceable processor configurations, and the next two bits are a good memory configuration

The states of these pairs of bits are decrypted by the decoder 37 of the processor state and the decoder 36 of the state of the memory block. At the same time, the processor and the memory block are connected to the interface according to the majority principle, if the specified pairs of bits are equal to code 00, with code

0 01 operation occurs from the first processor channel (memory block), with code 10 from the second channel, and with code 11 from the third processor channel (memory block)

In addition, all bits of the 17 stand counter with the counter 16 time slots in the device act as a watchdog timer, the overflow of which is used to form time stamps transmitted to the output

0 95 channels (in the absence of a signal at input 90 of the device), or to reset the device to its initial state by resetting it and setting code 11 at outputs 92.1 and 92.2 of the channel initial setup code (with a single signal at input 90 of channel ).

The use of a watchdog timer for device initial setup occurs when a specified time is allocated for executing individual subroutines. The failure of these subroutines is classified as a program failure, and the watchdog overflow causes the device to reset, and state 11 of the flip-flops 38 and 0

5 39 indicates the reason for the reset

To set the appropriate intervals of the watchdog timer, counters 16 and 17 record the corresponding codes set on one of the inputs of switch 1, since counters 16 and 17 can provide a reset signal at the output of the OR 72 element, these meters are reset output element OR 71

The instruction address counter 18 (data address counter 19) is intended for generating the instruction addresses (data) when accessing the memory or for addressing

0 elements of data arrays when moving them to memory.

The entry of the start addresses into the counter 18 (19) is performed as follows. Starting address code from groups 77 or 79

5 information inputs of the device through the switches I, the majority information block 44, the switch 2 and the buffer register 6 are fed to the information inputs D of the counter 18 (19), to the synchronous input. From which the sync signal is fed to the input 85 7 (85.10)

the recording signal of the first group of 85 control inputs of the channel, by which the starting address is recorded in the counter 18 (19). When the clock signal is fed to input 86.8 (85.11), the contents of the counter of the first group 85 of the control inputs of the channel are increased, the contents of the counter 18 (19) increase by one. The reduction per unit content of the counter 18 is produced by applying a signal to the input 85 9 of the group 85 of the device inputs.

Counters 18 and 19 are reset to the initial zero state by a signal from the output of the fifth element, OR 72.

To store the address of the next command in the memory, it is transmitted from the output of the command address counter 18 to the device information output group 83 via the switch 1, the majority information block 44, the switch 2 and the buffer register 6.

The transfer of command or data addresses from the outputs of counters 18 and 19 to the channel address output group 96 is performed via the address switch 27 and the majority address block 42. At a zero signal at the input 85.12 of the first group 85 of the control inputs of the channel, the contents of the command address counter 18 are transmitted via the address switch 27, and at a single signal, the contents of the data address counter 19.

The switch 20 states of the memory block is designed to transmit to the corresponding information inputs of the switches 24-26 codes of the state identifying the state of the first memory block, or from the outputs of the decoder 36 states of the memory block in the mode of initial setup of an operable block configuration a low signal level at the first control input 89 of the channel, or from the outputs of the first three-bit zone of the register of 12 states of the memory during the main operation of the device with a single signal at the first control input 89 Ala. It follows from the above that a sign of setting the device operation mode by initial setting up the correct configuration of the connected blocks or its main work on transferring information between the blocks via the interface is the absence or presence of a signal at the first control input 89 of the channel.

The switches of the first 21, second 22, and third 23 bits of the processor state are intended to transmit the state codes of the processor state to the corresponding information inputs of the switches 24-26, or from the outputs of the decoder 37 states

The percent process in the initial setup mode of the processor with a zero signal at the first control input 89 of the channel (the signal state at the output of the processor control rearrangement 48 in this mode does not affect the operation of the switches 21-23, because the outputs of the state decoder 37 the processor is connected to the first O and the second 1 information inputs of the switches 21-23), or from the outputs of the first register 14 processor states in the main operation mode of the interface with a single signal on the ground

5 of the control input 89 of the channel and the zero signal at the output of the majority element 48 of the processor reorganization control, or from the outputs of the second register 15 of the processor in the tuning mode is equal to the processor configuration when it fails in two channels, which is determined by a single signal state on the first the control input 89 of the channel and the output of the majority element 48

5 Table 4 shows the sources of information transmitted through the switches 21-23, and the conditions for transmitting this information.

The first 24, second 25 and third 26 state code switches are used to transfer the contents of the register of 12 states of memory or the code from the output of the state decoder 36 of the memory, the contents of register 13 of the air-blast state and the contents

5 of the first register of 14 states of the processor, or information from the outputs of the decoder 37 states of the processor, or code from the outputs of the second register 15 of the processor, or a zero code (state

0 tires of zero potential) for the first inputs of the fourth 63, p 64 and sixth 65 elements, respectively, And, and the inverse values of these codes - on the first inputs of the first 60, second 61 and third, respectively

5 elements I. The selection of the information input of the switches 24-26 of state codes for transmitting information of the corresponding source is carried out by a code at the output of the code converter 34. With

0 transferring the contents of the control register 5, the command address counter 18 or the counter 16 time slots and the code source state counter 17 for transmitting the code through the switches 24-26 is

5, a potential-zero bus. Therefore, the information of these interface nodes is transmitted to its group 83 information outputs on a majority basis, and the means of control at the time of transferring their information can only allow the control of the processor by the second comparison unit 73.

The transmission of information from the corresponding source through the device (and, respectively, through the input information switch 1) is accompanied by the generation of the corresponding signals on groups 85.3 and 85.13 of the channel control inputs, the higher bits of the group 96 address outputs of the channel and on the group 97 outputs of memory control signals ( It is assumed that the high bits of the group of 96 address outputs of the channel provide for the selection of one of the n memory blocks, and the lower bits - the corresponding cell of this memory block).

These signals are converted by block 34 to switch control code 24-26 in accordance with Table 5.

The switch 29 of the overflow signal of the 17 state counter is intended for the element 47 to transmit the overflow signal of the counter 17 to the output 95 of the channel time stamps with a zero signal at the second control input 90 of the channel or to the third input of the fifth element OR 72 and to the second inputs of setting a single signal to the second control input 90 of the channel. Thus, under control of the signal at the channel input 90, either the device is reset to produce a code 11 at the outputs 92 1 and 92 1 of the channel, or a signal is formed at the output 95 e channel which can be used to interrupt operation of the device

The switch 30 of the overflow signals of the counter 16 time intervals is designed to provide the counting input of the 17 state counter and the inverse input of the second element OR NOT 59 clock signals or from the overflow output of the counter 16 time intervals when the output signal of the first element OR NOT 58 is zero, or from the output of block 31 start counters connected to the counting input of the counter 16 time intervals Thus, the switch 30 adjusts the frequency of the clock signals on the counting input of the counter 17 and the inverse input of the element OR NOT 59 which a is either equal to the frequency of the clock signals at the input91 of the channel, or reduced by a factor of 2g, where g is the counter width of 16 time slots. The different frequency of changes in the state of counter 17 (the frequency of reconfiguration of the processor and the first memory block during the initial setup of a good configuration of connecting them to the interface) is determined by the condition of forming the reset signals at inputs 87.1 and 87.2 of the channel reset. When a device channel is reset by a signal received at its input 87.1,

the clock signals to the counting input of the counter 17 come from the overflow output of the counter 16 ,. when the channel is reset by the signal received at input 87 2 of the device, the sync signals to the counting input of counter 17 are received from the output of the meter start block 31, the counter of 16 time slots (provided by a low level of the signals at the output of the AND-HE element 57 and input 89

0 channel)

The block 31 of the start of the counters (see figure 4) is designed to enable or block the passage of clock frequency signals from the input 91 of the frequency of the master oscillator of the channel

5 With a low signal level at the first control input 89 of the channel (initial setting mode of a workable interface configuration and blocks connected to the interface), the clock signals

0, the frequencies from the device input channel 91 to the output of the meter start block 31 are transmitted unconditionally, since the high level of the signal at the output of the element NE 130 opens the second gate of the element AND-OR 129.

5 When the signal level at the first control input 89 of the channel is high, the second gate of the AND-OR element 129 is closed and the frequency pulses of the master oscillator from the channel input 91 to the output of the meter start block 31

0 are transmitted only when trigger trigger 128 is turned on. At initial device reset, a trigger 128 is set to the initial off state by a signal from the output of the fourth element 5 OR 71 To trigger trigger 128, a single signal is sent to its information input D, and to sync input C of trigger 128, a sync signal from the fourth input 85.17 synchronization of the first group of 85 managers

0 channel inputs

The first comparison unit 32 is designed to compare the information of two adjacent channels and generate a zero signal at its output with equal information and a single signal - if the information of the two channels is unequal

The switching control blocks 33 (Figs. 1 and 3) are intended for switching signals generated at the outputs of the majority elements 91.-93 of the block 9 majority elements in order to convert these signals (depending on the state of the respective three-digit zones of the state register 12) identical in all

5 three channels, to the corresponding various three-channel control signals of the switch 2 output information This conversion occurs when transmitting through switches 24-26 codes equal to 100, 010 or 001, which require rebuilding of various channels of the device to transmit information from only one of three remaining serviceable source information block. In this case, at the outputs 114 and 115 of the switching units 33, codes are formed in the three channels of the device in accordance with Table 6.

The decoder 35 of failures converts the codes of the results of comparisons into the inverse value of the unitary code identifying the failed channel in accordance with Table 7, with a zero signal at the output of the first element AND-OR-NE 49 when at least two channels of the source information blocks of the monitored information are intact. With a single value of the signal at the output of the first element AND-OR-NO 49, when there is a failure in at least two channels of the source information blocks of the monitored information or when the device is operated channel by channel (the information of each channel is transmitted independently of other channels), the decryption is No signals at the information inputs DcrD2 of the decoder 35 of the failures are blocked.

The assignment of the state and memory processor 37 decoders consists in converting the codes of the corresponding zones of the state counter 17 (see the explanation of the operation of the state counter 17) into unitary three-digit codes that control the processor and memory block during initial configuration of the serviceable configuration devices, i.e., with a zero signal at the first control input 89 of the channel. With a single signal state at the input 89 of the channel (the mode of the main operation of the device), the decoders 36 and 37 do not participate in the operation of the device, therefore their This does not matter in this mode.

The first 38 and second 39 reset triggers are designed to capture and indicate the signals of the initial installation of the device. The states of the flip-flops 38 and 39 can, firstly, identify the history of the operation of the device, secondly, be used to store in the counter 18 command addresses of the initial addresses of the subroutines corresponding to each of the signals of the initial installation. Four instances of the initial installation are provided in the device, each of which is determined by the corresponding signals.

1. The start of operation of the device is preceded by a reset signal, which enters the device at the first reset input 87 1 (which is set by reset triggers 38 and 39 to state 1). It enters the outputs of the fourth 71 and the first 72 elements OR, sets all the elements of the device memory to its original state. In addition, the signals from the output of the pth element OR 72

receive the channel reset output 94 to reset the blocks connected to the device.

In this case, a single potential is generated at the output of the fourth element IS-57 57, and the output of the first element OR-NOT 58 produces a zero potential at which the output of the switch 30 will receive signals from the counter overflow output of 16 time intervals, i.e. . The frequency of the signal input to the counting input of the 17 state counter and the inverse input of the second element OR NOT 59 is 2 times less than the frequency of the master oscillator signals at the input 91 of the channel. After receiving the device reset signal on the first input 87.1 reset, the device starts operation in initial setup of a good configuration of interfaced blocks matching, as will be described below

52 When a device encounters abnormal situations during operation, resulting in distortion of information both in the device itself and in the blocks associated with it, for example, short-term

0 voltage drop across the power supply circuit, setting the device to the initial state and its initial setting starts at the signal coming in via the second input 87 2 channel reset Difference effect

5 the device of this signal from the one described above is that it is identified by the state 01 of the flip-flops 38 and 39, respectively. At the output of the fourth AND-NOT 57 element, a zero potential is formed, and at the output of the first OR-NOT 58 element, the unit potential, Since at the first control input 89 of the channel there is a zero potential until the interface is tuned to the correct configuration of external units. With a single signal at the output of the first element OR NOT 58, the switch 30 transmits signals to the counting input of the counter 17 states and to the inverse input of the second element

0 OR-NOT 59 signals from the output of the meter start-up block 31, and not from the overflow output of the counter 16 time intervals The frequency of the signals at the output of the switch 30 is equal to the frequency of the signals of the master oscillator at

5 input channel 91, so setting up the device to a healthy configuration when unauthorized interruptions of its operation occurs 2 times faster than when setting up before the start of the main operation, which is especially important

when the device is operated in a process control loop, the termination of which is economically unprofitable, or when the device is operated in medical equipment that could affect human health.

3. The search for a valid configuration, interfaced to the interface of the blocks (control of the health of the blocks, for example, testing, is provided by the blocks themselves, the transfer of information between them is carried out by the interface, and if the test results do not have the control results, the interface automatically changes the configuration of the connections between the processor and the memory block under test, generates a reset signal at the output of the fifth element OR 72, resets the corresponding memory elements of the interface, generates a reset signal SA at channel output 94 and continues to work from this initial state determines the frequency of the signals at the output of switch 30, which are input to the fifth element OR 72 through the second element OR NOT 59 and the first major element 46 of the initial setup. This signal does not change the state of the first 38 and second $ 3 flip-flop triggers, therefore the cycle of operation repeats with its previous state and proceeds as described above. The differences here are only the state of the first four bits of the 17 state counter, which determine the configuration of the connections of the processor and the unit with the interface in the initial setup mode, as will be described below.

4. In case of emergency situations such as leaving the program (monitoring the progress of the program is done by the watchdog timer — counters 16 and 17 of the device, into which settings are set, determining the execution time of each program or subprogrammes) when the next setpoint before the counter 17 overflows entered, an overflow of counter 17 occurs, and its overflow signal, having passed through the second major element 47 of the initial installation and the switch 29, arrives at the corresponding inputs of the fifth element OR 72 and the first 38 and the second 39 trigger In this mode of operation, a high level signal is present on the first control input 89 of the channel, therefore the device operation in this case is determined by the state of the registers 12-15, and not by the state of the counter 17. With these soft failures of the type of failures (failures) in the program the program is changed by entering

corresponding codes in the counter 18 addresses of commands. Thus, the state of three 11 failures 38 and 39 of failures determines the situations occurring in the device.

Installing flip-flops 38 and 39 reset o

the initial state 00 is produced by a signal on the second input 85.16 of the installation of the first group 85 of the control inputs of the channel.

0 The first processor reorganization trigger 40 controls processor rebuilding in the event of a second failure (processor failure in two channels). A sign of a second failure recorded by the interface is

5, the second trigger of the processor rearrangement control 41 is turned on, and the indication that the failed block is a processor is a signal at the output Qe of the fault register 5. In this case, at the exit of the eighth

0 of the element 67 and 67, a single signal is generated which, via the majority element 48, controls the reorganization of the processor, arrives at the information input D of the first reorganization control trigger 40

5 of the processor and entered into it at the falling edge of the signal at its synchronization input C. The sync signals for trigger 40 are pulses at the input 91 of the frequency of the master oscillator of the channel

0 The single state of the signals at the output of the major element 48 (second processor failure) and at the output of trigger 40 (the second processor failure is synchronized by the clock signal

5 nerator) permits the passage of these sync signals (full signals in all three channels that could have been formed in the absence of trigger 40) through the seventh element 66 and the third element

0 OR 70 per clock input C of the second register of 15 states of the processor, which in this case operates in the ring shift mode.

The trigger 40 is set to its initial zero state by a signal from the output of the fifth element OR 72.

Setting the trigger 41 to the initial zero state is performed simultaneously with resetting the register 5 of failures (see above),

0 and the installation in the single state will be described below when explaining the operation of the AND-OR 50 element.

The majority address block 42 (control) is used to transfer address (control signals) to a group of 96 address outputs (group 97 of memory control signals) from the outputs of address switch 27 (group 101 of channel memory control signals) by the majority principle (2 out of

3) or with the restructuring of block 42 (43) to transfer information from any one channel to three channels or per channel. The reorganization of the majority blocks 42 and 43 is performed by signals from the inputs 86.1-86.3 of the second group 86 of the control inputs of the channel.

When transmitting signals through the majority block 42 (43), 2 out of 3 to the input 86.1 of the simulation O group 86 of the channel inputs receive the potential of a single signal, to the input 86.2 of the simulation 1 and the first input 86.3 of the channel operation selection are the potentials of zero level. In this case, the outputs of the majority blocks 42 and 43 generate signals whose value is equal to the value of the two signals of the same name from the three channels at the inputs of the blocks 42 and 43, which corresponds to their work according to the majority principle.

To transmit signals from the outputs of the address switch 27 (channel inputs 101) of one device channel at the output of blocks 42 (43) of all three channels of the device, it is necessary to organize in this channel the operation of block 42 (43) in a majority mode, as mentioned above, in another channel at inputs 86 ,, 82.2 and 86.3, groups 86 should have the value 000, and in the third channel - the value 110.

The status of the signals at the inputs 86.1-8.63 of the group 86 in all three channels of the device when transmitting information from the first, second or third channel to the three channels is explained in Table 8.

To transmit the addresses of the control signals (to the outputs of the majority block 42 (43), the signals at the inputs 86.1-86.3 of the group 86 should be 101 in all three channels).

In order to issue to the outputs of the majority blocks 42 and 43 of the corresponding channel of the device of potential signals of a logical zero or logical unit at the inputs 86.1, 86.2 and 86.3 of the group 86 of the inputs, the codes 001 and / or 111, respectively, must be set in the corresponding channel of the device,

Thus, the majority elements of blocks 42 and 43 provide for the conversion of input signals according to the majority logic, the transmission of signals from any one channel to all three channels of the device, as well as channel-by-channel signal transmission. This ensures both the transmission of functional signals from the outputs of the switch 27 and the inputs 101 of the device, and the transmission of potential signals from a logical zero or logical unit, which makes it possible to organize a complete check of the majority elements in the presence of those in the memory blocks.

The majority information block 44 is designed to transfer information from the outputs of the input information switch 1 and inter-channel inputs 81 and 82 of the channel to the corresponding input of the switch 2 according to the majority principle.

The majority elements 46-48 pre0 are assigned to transmit the corresponding signals according to the majority principle.

The first element l / 1-OR-NE 49 is designed to control the operation of switch 2 (through blocks of 8 valves and 9 major elements, as well as through switching control unit 33 - through the inputs S0 and Si of switch 2) and to block the operation of the decoder 35 of failures if there are failures in more than one channel of the corresponding block, we consider the operation of the first element AND-YLI-NE 49 when describing the purpose of the AND 60-65 elements.

The element AND-OR 50 is designed to enable the second trigger 41 of the control

5 processor restructuring in case of processor failure in two channels. A sign of failure in more than one channel of the device is the single state of the first QI, the second Q2, and the third Oz of the outputs of the register 5

0 failures or the presence of a signal at least at one of the outputs of the Qi-Oz register 5 failures leading to the formation of a signal at the output of the first element OR 68, and the presence of a single signal at the output of the QS register

5 failures, which is written to register 5 from the output of the third AND-NE 56 element.

The second 51 - the fourth 53 elements AND-OR-NOT are designed to transmit the reverse state of the control signals from the corresponding outputs of the control decoder 35 to the information inputs Di-Da of the control register 5 with no signals at the outputs, respectively, of the first 60,

5 of the second 61 and third 62 And elements, if through the switches 24-26 information is transmitted not from the zero potential bus, or with a single state of the outputs of the switches 21-23 (no signals on

0 outputs of the block 76 of elements HE), if information is transmitted from the zero potential bus through switches 24-26 (in the first case, signals from the outputs of elements 60-62 are transmitted through switch 3, and

5 second - from the outputs of the switches 21-23 through the block 76 elements NOT). If there is a signal at the output of the first (second or third) element AND 60 (61 or 62) or at the outputs of the block 76 elements NOT the output signal AND-OR-HE 51 (52 and 53) sets a low level signal, i.e. the recording of the results of the control of the corresponding channel into the register 5 is blocked. This is done when registers 12-14 have already recorded the failure of this channel of the source information block.

If a block 32 or 73 fails in any channel at output 3, 5 or 6 of the failure decoder 35, a low level signal is generated, which is inverted by the first AND-54 element and stored in control register 5. After the information about the failure of the monitoring means in the register 5 of the monitoring control 5 is stored, the unit state is permanently established at the output of the NAND 54 element, which eliminates the loss of information about the failure of the monitoring controls.

The second element IS-NOT 55 is designed to transmit with the invert clock signal from the first input 85 1 of group 85 to the synchronized input of register 5 of the control, if it does not record the failure of any block, i.e. at its outputs Qi-Oz and, accordingly, at the output of the first element OR 68, there are no signals.

The third I-DAY element 56 is designed to generate a signal if at least one channel of the source information block is fixed with the corresponding register code 12, 13 or 14. The signal from the output of the AND-HE element 56 is stored in the fifth bit of the control register 5 in the presence of a unit at least at one of the outputs of the SIS Register 5 (and, accordingly, at the output of the first element OR 68) it ensures the operation of the AND-OR 50 element and the activation of the trigger 41.

The fourth element AND-NOT 57 forms a zero signal at the second input of the first element IL AND-NE 58 only in the state 01 of the flip-flops 38 and 39 of the reset. The first element OR NOT 58 forms a single signal at the control input of the switch 30 only at low signal levels at the output of the fourth element AND-NOT 57 (the device was preceded by a reset signal at the second channel reset input 87.2) and at the first control input 89 of the channel (the device works in the mode of setting up serviceable configuration of the units interfaced with the interface)

The second element OR-NOT 59 is designed to generate device reset signals in the initial setting mode (low signal level at the first control input 89 of the channel) when sync signals appear at the output of the switch 30 of the overflow signals of the counter 16 time intervals (during the block testing time the norm control results).

The first 60, second 61 and third 62 And elements are designed to transmit the inverse, and the fourth 63, fifth 64 and sixth 65 And elements are intended to transmit the direct value of the first, second and third bits of the corresponding zones, register 12, respectively, or the registers 13 -15,

0 or outputs of the decoders 36 and 37 and 24, 25 and 26 status codes transmitted through the switches, respectively, when the device is operated in the majority-redundant mode, i.e. at high level

5 signals at the second input 86.4 per channel operation of the second group 86 of the control inputs of the channel. At a low signal level at the input 86.4 of the group 86 channel inputs, zero signals are formed at the direct outputs of all elements 60-65, the inverse outputs of the elements 63-365 are single signals, and the output signal of the element AND-OR-NE 49 forms a single signal , and at the outputs 114 and 115 of the switching units 33

5 all channels - zero signals, which configures switches 2 in all three channels of the interface to transfer information from the outputs of the switches 1 input information (channel-by-channel mode of operation).

0 When the device is operated in the majority-backup mode, the direct outputs of the fourth 63 - sixth 65 elements And form codes in accordance with Table 2, and the outputs of the first 60 - third 62 And elements - inverse values of these codes. If there is a failure in any channel {0 in Table 2), a single signal is generated at the output of the corresponding element I 60-62, transmitted through switch 3 and

0 providing a zero signal to the output of the corresponding element AND-OR-HE 51-53, regardless of the state at the corresponding output of the decoder 35 control, i.e. blocking

5 control this channel. Hence the first purpose of the elements And 60-62. The second purpose of the elements And 60-62 - to ensure the transfer of information through the interface for 2 of 3 in the presence of failures

0 in the three channels of the source units of the dacha for the device (see the last row of Table 2). In this case, the single signals at the outputs of all three elements AND 60-62, connected to the inputs of the first valve of the AND-OR-HE 49 element, provide a zero signal at its output, through which information is transmitted through the device through 2 of the 3.

With serviceable blocks of information sources in at least two channels (see

The first four lines in Table 2) the signals at the direct outputs of the AND 63-65 elements according to the majority principle ensure the generation of a zero signal at the output of the AND-OR-NE 49 element, which also provides data transmission through the interface over 2 of the 3.

With serviceable information source blocks, only one of the channels (see, fifth, sixth and seventh lines in Table 2) at least one of the inputs of each valve of the AND-OR-NE 49 element contains a zero signal. Therefore, a single signal is generated at the output of the AND-OR-NO 49 element, which, firstly, blocks the operation of the fault decoder 35 and, accordingly, of the control means (with a single signal at input V of the decoder 35, single signals corresponding to the absence of faults are generated) secondly, it ensures the operation of the device, as described above,

The first element OR 68 is intended to form a signal at the first output 84.1 of a channel interruption requirement in the presence of at least one channel, i.e. in the presence of a single signal at least at one of the outputs of the CH-Oz register 5 control. In addition, a single signal at the output of the first element OR 68 allows the trigger 41 to be activated (with a single signal at the output 05 of the control register 5) and blocks the transmission of the sync signals to the synchronous input of the control 5 via the AND-HI element 55.

The second element OR 69 is designed to reset the register 5 of the control and the second trigger 41 to control the processor tuning by signals from the output of the fifth element OR 72 or from the first input 85.2 of the reset of the group 85 of channel inputs.

The third element OR 70 provides for the synchronization of the second register 15 states of the sync processor from the output of the seventh element And 66 and from the second input 85.14 sync signals of the group 85 of control inputs of the channel.

The fourth 71 and fifth 72 OR elements are intended to form the reset signals of the corresponding memory elements of the device. In this case, the fourth element OR 71 clears the register of 12 states of the memory, the first register of 14 states of the processor, counters 16 and 17, and the block 31 of the start of counters only when the reset signals are received at inputs В7.1 and 87.2 of the channel. The fifth element OR 72 resets the remaining memory elements of the device in addition to the above-described signals and signals from the outputs of the majority element 46 and the switch 29. As the counters 16 and 17 and the block 31 start counters are involved in generating these additional device reset signals,

therefore, these signals are not used to reset the same counters 16 and 17 and the meter start-up block 31.

Although the registers 12 and 14 of the memory and processor do not participate in the generation of additional device reset signals, they are not reset by these signals, since they record the information on the state of the blocks during the initial setup of a good configuration of the blocks connected to the interface.

We describe the operation of the device as a whole. During the operation of the device, it can be put into operation on and off at the end of the operation. During the whole period of operation, its nodes and blocks, which are joined to the interface, can fail both during work and during work breaks. Therefore, the operation of the device proceeds as follows.

The start-up of the device starts by resetting its nodes and the blocks joined with it by a signal arriving at the first reset input 87.1.

0 channels (reset flip-flops 38 and 39 are set to state 10) After that, the device and the blocks joined with it start operation, and the operation begins with testing the state of these blocks (signal

5 low level at the first control input 89 of the channel), and the 16 time interval counter sets the testing time during which the result of the control norm should be obtained with a single signal applied to the input 89 of the channel. This time is set by recalculating the frequency pulses of the master oscillator received to the input 91 channel. In the absence of a monitoring control time limit (a single signal at the channel input 89 is missing), the overflow signal of the 16 time intervals from the output of the switch 30 resets the device’s memory elements (except for the 16

0 and 17, registers 12 and 14, block 31 of the start of the counters and flip-flops 38 and 39), changing by one the least significant bit the state of the counter 17. Next, the operation of the device and the blocks joined with it is repeated first and

5 repeats cyclically until a properly configured configuration of interfaced blocks is automatically selected. The configuration of the blocks is determined by the contents of the four lower-order bits of the 17 state counter, decoded by the decoder 36 and 37, the codes from the outputs of which are transmitted through the switches 20-26, elements AND 60-65, element AND-OR-NE 49, block 8 of valves , the major elements 9.1-9.3 and the switching unit 33 to the control inputs of the switch 2, which determine the mode of data transmission via the interface, Table 9 shows the correspondence of the switch 2 operation to the codes of the four lower bits of the 17 state counter d counter 17 for the first bit d ).

The initial state of the lower four bits of counter 17 is code 0000, their final state is code 1111, after which these bits of counter 17 go back to state 0000. Overflow of state counter 17 generates a signal at output 95 of the device ( the overflow signal passes through the majority element 47 and the switch 29 at the zero signal at the input 90 of the channel) and means that there is not a single workable configuration of the device and the blocks connected to it

From the codes of Table 9 it can be seen that the operation of the controls in the configuration mode of a working configuration is blocked,

When receiving the rate of control results, a single signal is sent to the first control input 89 of the channel, the contents of the state counter 17 is read to the output 83 of the channel through the switch 1, the majority block 44, the switch 2 and the register 6, and the first zone of the memory register 12 and The first register of 14 processor states is entered into codes, as indicated in Table 10, according to the states of the lower bits of counter 17 (codes 1t1 are entered into the zones of the memory register of the second to the last and register 13 of the UVB states) ).

The control of the operation of the remaining blocks of memory and the air-blast is performed using the means of controlling the interface, similar to the operation of its main function

The operation of the device is carried out according to the program defined by the contents of the counter 18 command addresses, while the inputs 86.1-86.6 of the group 86 of inputs are given the code 100111, which ensures that the majority blocks 42 and 43 operate in the majority mode.

The comparison results by the comparison blocks 32 and 73 transmitted via the interface are converted by the decoder 35 of the failures and the elements I-1 / 1LE-NOT 51-53 and AND-NOT 54 into the corresponding channel failure codes stored in register 5 of the control. In this case, the first to third bits of the register 5 control identify the failed channel, the fourth bit records the failure of the control means, and the fifth - mth bit identifies the failed blocks in the channel.

The presence of a failure in any channel leads to the formation of a demand signal at the first output 84.1 of the channel interruption requirement, and the codes of the register 5 control

0 are used to enter the corresponding codes (see Table 2) into the three-digit zones of the respective registers 12-15.

Since the device blocks the control of the failed block and at two remaining healthy blocks their operation occurs in 2 out of 3, the replacement of the failed block can occur during the main operation of the device with the corresponding code entered in the register of 12-15 blocks

In case of failure of the equipment of the same name in two channels of the device, it operates in the mode of information transfer from a healthy channel to three channels of the device.

5 when operating the device with the aforementioned equipment in accordance with the above, and it is prohibited to monitor all three channels of this equipment.

The independent operation of the three channels of the device is determined by applying code 101011 to the inputs 86 1-86 6 of the group 86 inputs in all three channels of the device, while the device controls the operation

5 If during the operation of the device an unauthorized situation occurs, such as a power failure, and if it is critical to set up the device for a good configuration for

0 continue operation, the device starts operation with a signal to the second channel reset input 87.2. In this case, the period of change of the states of the counter 17 is determined by the frequency of the pulses of the master oscillator at the input 91 of the channel, and not by the frequency of the counter overflow of 16 time intervals. The rest of the operation of the device is similar to that described above.

0 To monitor the progress of the program, a watchdog timer is used in the device, which uses counters 16 and 17 and their start block 31. In this case, the codes entered in them determine the time of passage

5 of the program (subprogram), at the end of which new codes are entered into counters 16 and 17, which determine the time of the next program (subprogram). If the program has an error or failure, then during the control

,

time, no change of codes in the counters 16 and 17 will occur, and an overflow of the watchdog timer will reset the device and go to work defined by the 11th code on the outputs of the flip-flops 38 and 39 in 5 according to the above

If it is necessary to turn off the watchdog timer, the trigger trigger 128 is turned off in the start block 31 of the counters.

If it is necessary to interrupt the course of operation of the device when a given command is reached in the read-out mode of a coma, the words (the limit of the subprogram, beyond which there may be a defect in the program or beyond which a subprogram is required for some other reason) or when referring to the memory at a specific address in the read mode or the mode of writing data to the control register register 10, the corresponding mode code is entered, and the address register register register 11, the address code, when accessing which is required rmirovat signal interruption 25 Vani requirements. The moments of occurrence of one of the above-mentioned modes in the device are determined by the signals at the input 85,22 of the control of the decoder of the characteristics of the interruption of the first group 85 of the controllable 30 channel inputs. These signals are sent to the first control input of the interrupt feature decoder 75, which decodes the code of the corresponding mode in register 10 When accessing 35 to the corresponding memory address at the output of address comparison block 74, which compares the contents of register 11 with the address code at the output of address switch 27, a signal is generated that arrives at the AO second control input of the decoder 75. When all the specified conditions coincide, the output of the decoder 75 generates a signal arriving at the second output 84.2 of interrupt requests and both 45 ensures, interrupt operation.

The operation of the device proceeds under control of the signals supplied to the device through groups 85 and 86 of the control inputs and through the inputs of 87-91 channels, and the interface combines information transfer time into a group of 83 information outputs (in accordance with the law of external blocks) with the transfer of information to the internal 55 memory elements of the interface (registers, counters), and the processor is monitored not only at the moments when its information is transmitted through the interface, but also at those points in time, when

the transformation of information in the processor occurs without the transfer of information through the interface /

Thus, an increase in the control efficiency, and, accordingly, an increase in the interface setting speed for a workable configuration, is provided. In addition, it is possible to dynamically correct programming errors, which, in addition to improving the reliability of the device, reduces the cost of the computational tools of which the proposed device is a part.

An additional positive effect is an increase in the performance of the device, since time losses from the moments of detecting a processor failure to the moments of transmitting its information through the interface are eliminated.

Claims (1)

Claims of the Majority-redundant memory interface containing in each channel input, output and service information switches, control register, first and second buffer registers, valve block, majority element block including first, second and third major elements, block status register memory, I / O device status register, first and second processor status registers time counter, status counter, command address counter, Data address counter, status switch No memory block, first, second and third processor state switches, first, second and third status code switches, address switch, processor reconfiguration switch, time counter overflow signal switch, counter start block, first comparison block, switching control unit, code converter, fault decoder, memory block state decoder, processor state decoder, first and second reset triggers, first and second reconfiguration control triggers processors, majority address blocks, control and information, the first and second major elements of the initial installation, the major element of the control reconfiguration of the processor, from the first to the fourth elements AND-ILY-NOT, first to fourth elements AND-NOT, the first and second elements OR -NO, first through eighth elements AND, first through fifth elements IL, AND element IL-IL and processor reconfiguration control, the information inputs of the first to third groups of the input information switch are respectively the information inputs t processor, from the input / output device and from the channel memory block, the outputs of the input information switch are connected to the inputs of the first group of the first comparison block, to the information inputs of the first switch output group, to the inputs of the first group of the majority information block the outputs of the first channel group, the information inputs of the second group of the output information switch are connected to the inputs of the second group of the majority information block and are inter-channel inputs of the second channel group The inputs of the third group of the majority information block are connected to the information inputs of the third group of the output information commutator, with the inputs of the second group of the first comparison block and are inter-channel inputs of the first channel group, the outputs of the majority information block are from the fourth output switch group information, the outputs of which are connected to the information inputs of the first and second buffer registers, the synchronization inputs of which are the corresponding channel inputs, outputs The left buffer register is connected to the inputs of the first group of the service information switch, the inputs of the second group of which are connected to the information inputs of the command address and data address counters, with the outputs of the first buffer register and are the information outputs of the channel, the control inputs of the input and service switches channel inputs, service switch outputs; Connected to the inputs of the first switch panel of the processor’s reconfiguration, with information the first processor state processor, time counter, state counter, memory block status register, input / output device status register, and counter start block, the synchronization input of which is the corresponding channel input, clock input of the counter start block connected to the synchronization input of the first controller trigger of the reconfiguration of the processor, with the first input of the seventh element I, and is the frequency input of the master oscillator of the channel, the inputs of the installation of the meter start-up unit, the counter variable intervals, a state counter, a register of memory blocks and a first processor state register are combined and connected to the output of the fourth OR element, the first and second inputs of which are connected to the first and second inputs of the fifth OR element and to the first installation input and the second the reset input of the corresponding reset triggers, respectively, and are the first and second channel reset inputs, the first reset inputs of the first and second reset triggers are combined and are the second channel setting input, the second inputs are set and the first and second reset triggers are combined and connected to the third input of the fifth OR element and to the first output of the overflow signal switch of the state counter, the second output of which is the output of channel time marks, the outputs of the command address counter are connected to the information inputs of the fourth switch group input information and with the inputs of the first group of the address switch, the inputs of the second group of which are connected to the outputs of the data address counter, the installation input of which is connected to the inputs of the installation of the counter ad commands, the first processor control reconfiguration trigger, the second processor status register, the I / O device status register, the first input of the second OR element, and the fifth OR output, is the channel reset output, the second input of the second OR element is the first the channel setup input, the synchronization inputs, the decrement and the increase in the contents of the command address and data address counters are the corresponding channel inputs, the output of the meter start block is connected to the counting input of the time counter intervals and the first input of the switch overflow signals of the time counter, the second input of which is connected to the overflow output of the time intervals counter, whose information outputs are connected to the information outputs of the state counter and information inputs of the fifth group of the input information switch overflow time counter - with the output of the first OR-NOT element, the first input of which is connected to the control input of the counter start-up unit, the first input of second OR- NO element, to second inputs of the gate switches the first to third discharge state rows processor, a control input of the switch states of the memory block and is the first control channel input, a second input of the first element OR is NOT connected to the output of the fourth NAND element, the first and second inputs of which are connected respectively to the inverse output of the first and to the direct output of the second reset trigger, the forward outputs of which are the first and second outputs of the initial setup channel, respectively, switch output overflow signals of the time interval counter are connected to the counting input of the state counter and with the inverse input of the second element OR NOT, the output of which is connected to the first input of the first major element of the initial It is the second inter-channel output of the channel, the overflow output of the state counter is connected to the first input of the second major element of the initial installation and is the third inter-channel output of the channel, the synchronization input of the state counter is the corresponding input of the channel, the second and third inputs of the first and second major elements of the initial installation are the third and fourth, fifth and sixth interchannel channel inputs, respectively; the output of the first major element of the initial installation is connected with the fourth input of the fifth element OR, the output of the second major element of the initial installation — with the switch input of the overflow signal of the state counter, the control input of which is the second control input of the channel; the synchronization input of the first processor state register is the corresponding input of the channel; - the third outputs of the first register of the processor state are connected respectively to the inputs of the third bit of the switches of the first to third bits of the processor state, the combined inputs of the first and the second bits of which are connected to the corresponding outputs of the state decoder of the processor, the inputs of which are connected to the corresponding information outputs of the state counter, the first and third outputs of the second register of processor states are connected respectively to the inputs of the fourth bit of switches of the first to third bits of the state switches neither the processor, and the inputs of the second switch group of the processor reconfiguration, the outputs of which are connected to the information inputs of the second processor status register, the input is synchronous which is connected to the output of the third OR element, the first input of which is the synchronization input of the second channel processor status register, the second input of the third OR element is connected to the output the seventh element And, the second input of which is connected to the output of the first trigger control reconfiguration of the processor, the information input of which is connected to the third input of the seventh element I, with the control input of the switch of the processor reconfiguration, with the first control inputs of the switches of the first to third bits of the processor state and 0 with the output of the major control element of the reconfiguration of the processor, the first input of which is connected to the output of the eighth AND element and is the first inter-channel output of the channel, the second and 5 third inputs - respectively the first and second inter-channel inputs of the channel; the outputs of the switches of the first to third bits of the processor state are connected respectively to the inputs of the first bit of the first to third switches of state codes, the additional information inputs of which are connected to the zero potential bus, synchronization inputs the memory block and input / output unit status registers are the corresponding channel inputs, the outputs of the first to third bits of the state of the I / O device register Nena respectively with the second discharge inputs yes 0 of the first-third state code switches, the inputs of the state decoder of the memory block — with the corresponding information outputs of the state counter, the outputs of the state decoder of the memory block — with the inputs of the first group of the state switch of the memory block, the inputs of the second group of which are connected with the outputs of the first zone of the state register of the memory blocks, the outputs of the first - the third bit 0 of the state switch of the memory unit are connected respectively to the inputs of the third bit of the first and third switches of the state codes, the outputs of the first to third bits of the corresponding zones of the register of the five blocks of memory, except the first one, are connected to the corresponding inputs of the first to third switches of the state the control inputs of which are combined and connected to the output of the converter code, the information inputs of which are connected to the information inputs of the control register group, the outputs of which are connected to the information The inputs of the sixth switchboard group of the input information, the outputs of the first to third bits of the control register are connected to the inputs of the first OR element and to the inputs of the first gate of the processor's AND-OR control reconfiguration, the first input of the second valve of the register , the second input of the second gate of the element AND-OR is with the output of the first element OR, with the inverse of the input of the second element IS-NOT, and is the first output of the channel interruption requirement the first synchronization input of the channel, the output of the second element AND-NOT is connected to the synchronization input of the control register, the installation input of which is connected to the output of the second IL element and to the reset input of the second trigger of the reconfiguration of the processor, the installation input of which is connected to the output of the AND element - OR control of the processor reconfiguration, output of the fourth bit of the control register - with the inverse input of the first NAND element, the first to third inputs of which are connected respectively to the fourth, sixth and seventh outputs d the fault encoder, the first output of which is connected to the first inputs of the first valves of the second and fourth AND-OR-NOT elements, the second inputs of the first valves of which are connected respectively to the third, second and fifth outputs of the failure decoder, the information inputs of which are respectively the first the third inputs of the channel comparison code, the outputs of the second and fourth elements AND-OR-NOT and the first element AND-NOT are connected respectively to the first to fourth inputs of the bits of the control register, the input of the first digit of which is connected to The output of the third NAND element, the inputs of which are connected to the direct outputs of the fourth and sixth elements AND, the information outputs of the control register group are connected to the inputs of the first group of the eighth element AND, the inputs of the second group of which are connected to the output of the second processor control reconfiguration trigger my outputs of the first and third switches of state codes are connected respectively with the first inputs of the first and fourth, second and fifth, third and sixth elements AND, the second inputs of which are combined and are the input of the channel operation selection, the outputs of the first and third elements AND are connected to the inputs of the first valve of the first element AND-OR-NOT, the inputs of the second-fourth valves of which are connected in a major scheme to the direct outputs of the fourth and sixth elements AND, respectively, inverse the outputs of which are connected to the inputs of the valve block, the first to third outputs of which are connected to the first inputs of the first to third major elements, respectively, and are the fourth to sixth interchannel channel outputs, the second and third inputs of rzogo-third majority elements respectively vlchyuts seventh and eighth, ninth and tenth, eleventh and twelfth channel inter-channel inputs, the outputs of the first to third majority of elements are connected to the control unit switching inputs whose outputs 0 is connected to the control inputs of the output information switch, the control input of the fault decoder — to the output of the first AND-OR-NOT element and to the first control input of the valve assembly, the second and third control inputs of which are the inputs of the second group of unit simulation and channel zeros respectively, the control address switch input is the corresponding channel input, the outputs The 0 address switch is connected to the inputs of the first group of the majority address block, the inputs of the second and third groups of which are the third and fourth groups of inter-channel channel inputs, the outputs of the first group of the majority address block are the second group of inter-channel outputs, the outputs of the second group of the majority address block are connected With the corresponding information inputs of the code converter and is a group of address outputs of the channel, the group of control inputs of the code converter is a group of inputs the operation of external channel blocks that control The 5 inputs of the majority address block are connected to the control inputs of the majority control block and are the inputs of the first simulation group of zeros and channel units and the first input of the channel operation selection, respectively, the inputs of the first to third groups of the majority control block are respectively a group of control inputs of the memory these channels and the fifth and sixth groups of inter-channel inputs of the channel, the outputs of the first group of the majority control block are the third group of inter-channel outputs of the channel, the outputs of the second group of m zhoritarnogo control unit coupled to corresponding inputs 0 code converters and is a group of outputs of the channel memory control signals, the inter-channel outputs of the first group of the first channel are connected to the inter-channel inputs of the second and first groups of the following 5 channels, respectively, the outputs of the comparison results of the first to third channels are connected to the first to third inputs of the comparison code of the first to third channels, respectively, the interchannel outputs of the second and third groups of each channel, respectively, to the interchannel inputs of the third and fifth groups of the next channel, which are connected to the interchannel channels, respectively the inputs of the fourth and sixth groups of the next channel, inter-channel outputs from the first to the sixth channels of each channel are connected respectively to the first, third, fifth, seventh, ninth "The eleventh inter-channel inputs of the next channel, which are connected to the second, fourth, sixth, eighth, tenth and twelfth inter-channel inputs of the next channel, the inter-channel outputs of the fourth group of the first channel are connected to the inter-channel inputs of the fourth group of the third channel, the inter-channel outputs of the fourth group of which are connected to inter-channel outputs the inputs of the seventh group of the first channel, characterized in that, in order to increase the reliability of the interface by increasing the efficiency of monitoring emerging failures, the adapta interface to failures and provision of dynamic program correction, a control interlock switch, an interrupt symptom control register, an interrupt symptom address register, an AND-OR-NOT control control element, a second comparison block, an address comparison block, an interrupt indication decoder, and a block of JHE elements, the inputs of which are connected to the outputs of the switches of the first to third bits of the processor state, the outputs of the first to third elements of AND are connected to the inputs of the first block of the control lock switch, in Odes of the second group of which are connected to the outputs of the block of NOT elements, the outputs of the control lock switch are with the first and second inputs of the second valves of the second to fourth elements AND-OR-, respectively, the control input of the control lock switch is connected to the output of the code converter, the inputs of the first switch group input information is connected to the inputs of the first group of the second comparison unit and is the fourth group of inter-channel outputs of the channel; the inputs of the second group of the second block comparisons are the seventh group of inter-channel inputs of the feces, the output of the second comparison unit is connected to the first input of the first gate of the AND-OR-NOT control control element, the first input of the second the gate of which is connected to the output of the first comparison unit, the second inputs of the first and second valves of the AND-OR-NOT control control element are respectively the first and second control inputs of the channel control, the output of the AND-OR-NOT control control element is the output of the channel comparison results, the information inputs of the interrupt indication address register and the interrupt indication control register are connected to the information inputs of the I / O device status register, the installation of which is connected to the installation input interrupt control register indication, clock inputs of the register control and indication interrupt address tag register and interrupt the first control input of the interrupt decoder features are relevant the channel inputs, the outputs of the control register for the indication of the interrupt and the address register of the characteristic of the interruption are connected to the information inputs of the fifth group of the input information switch, as well as to the inputs of the interrupt feature tracer and to the inputs of the first group of the address comparison block, respectively, the inputs of the second group of the address comparison block are connected to the outputs of the address switch, the output the address comparison unit is connected to the second control input of the interrupt feature decoder, the output of which is the second output of the channel interruption request. Table 1  The device is operational and will function correctly if J-1 bit of the 1st memory block has a failure in no more than one channel (I 1. n and j 1, N. where N is the difference of information words transmitted through the interface). table 2 X - signal state is indifferent. X - signal state is indifferent. Table 3 Table 4 Table 5 X - state is indifferent. Table 6 Table 7 Table 8 10,000 about about about 1 J o o 1 o  about -o 1 50100 60101 7 0 1 80111 91000 10 1О О 1 II 1 0 1 About 12 101t 13 1 1 00 I 1101 15 I1 1 O 16 tIIt Continued table. eight Pereyaya information processor and Pamp-ti on 2 out of 3 The transfer of information prospore first canapes three channels, put “in memory 2 Information transfer of the processor of the second channel and three channels (and of the Memory Block - 2 out of 3 Information transfer of the third channel processor in three channels, and the memory block - 2 and 3 of each Transferring processor information for 2 and 3, in the memory block - the first channel in three channels Transmission of information of the processor and memory block on the first channel of a fpn channel Transmission of the atri of the channel by the in- formation of the second channel of the processor and of the first channel to the controllers Transfer to three channels, information from the Third Channel of the processor and the first channel of the memory block Transmission of information processor 2 for 3, and the memory block of the second channel and three channels Transfer to three channels information from the first channel of the processor and the second channel of the memory block Transferring processor and memory information from the second channel to three channels Transfer to three channels of information from the third channel in the processor and the second channel of the memory block Transmission of information of the processor by 2 to 3, and the memory block - the third channel of the ASA TP (th Channel) Transfer three information channels from the first channel of the processor and the third channel of the RaMnrer block Transfer to three channels of information e of the second channel of the processor and the third channel of the memory block Information transfer of the processor and the memory block of the third channel to all three channels Table 10 (O 0 yy- fm Јrgd Fi. 18 Phage L