SU1739452A1 - Control gear for variable ac-to-ac voltage transformer - Google Patents

Abstract

SUMMARY OF THE INVENTION: A variable voltage-to-AC variable voltage converter control device includes network voltage sign indicators, a switching voltage sign indicator, a network voltage and switching voltage signs coincidence indicator, and a phase control unit. The switching of the transformer branches is carried out by the joint operation of the thyristor switches and the mechanical switch of the branches, or by using only the thyristor switches within the limits of the transformer control winding stage. The moving contacts of the mechanical switch alternately switch odd and even branches without current. A phase control unit generates the control pulses of the thyristor switches synchronized with the supply voltage. 3 or

Description

The invention relates to the field of electrical engineering and can be used to control an adjustable AC-to-AC converter operating under load, in particular, to control the regulation of the supply voltage of non-ferrous metallurgy and chemical industry electrolysis / converter plants.

A three-phase voltage transformer with phase voltage control is known, comprising a mains winding, a control winding and switching devices.

with moving contacts on each of the transformer phases.

The disadvantages of this device are large weight and size parameters due to the use of three switching devices and a low switching resource limited by the electrical durability of mechanical contactors.

It is also known to have a device for regulating the voltage of a three-phase transformer, which contains three single-phase switches that carry out phase-by-phase regulation.

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The disadvantages of this device are large weight and size indicators due to the use of three single-phase switches with separate actuators and a low switching resource.

An adjustable variable-to-variable voltage converter is known, which contains a transformer, a regulator in the form of several groups of thyristors, a pulse generator, a synchronized voltage of the network, a block of elements And, a reversible p-discharge counter, a comparator, a voltage sensor controlled by k -discharge frequency divider and D-trigger.

The disadvantages of this device are large weight and size parameters with a large up to 100% voltage control range due to the need to use a large number of thyristors with coolers, constant switching of the thyristors without performing voltage control of the transformer, causing additional power loss and heating of the thyristors, deterioration of quality parameters power supply network when using the number-pulse method of voltage regulation.

The closest to the invention to the technical essence is an adjustable AC-to-AC converter that contains AC thyristor keys, some of which are connected via the moving contacts of a Mechanical switch to the transformer windings, and the other to the extreme leads of current-limiting reactors, the middle terminals are connected to the terminals of the corresponding phases of the mains supply, the thyristor control pulse drivers, the network voltage sign indicators and the commutator voltages with positive and negative signs, a voltage matching indicator of the network voltage of a switching voltage of one phase, a network voltage synchronization unit, the inputs of which are connected to the outputs of a network voltage sign indicator, with control circuits Above, Below, with the outputs of the indicator of coincidence of the signs of the network voltage and the switching voltage, and the outputs of the synchronization unit are connected to the corresponding thyristor control pulse driver.

The disadvantage of the known variable voltage alternator in

variable is the low control accuracy due to the inability to control the voltage within the control step of the transformer winding.

The aim of the invention is to improve the accuracy of regulation.

The goal is achieved by the fact that the device for switching transformer under-load taps is equipped with a phase-control unit, including a clock pulse generator, the first and second two-input AND – NES elements, a binary reversible counter, a decoder with seven inputs and seven outputs, realizing the corresponding output with input signals in accordance with the truth table shown in FIG. 4, the time relay, the first, second and third two-input elements OR-NOT, the first, second and third D-triggers, the first and second two-input elements And, the first and second inverters, the first and second JK-triggers, and the third and fourth the decoder inputs are designed to provide them with Higher signals. Below and connected respectively to the first inputs of the first and second two-input elements And, as well as to the first and second setting inputs of the time relay, the output of the clock generator is connected to the first inputs of the first and second two-input elements AND-NOT and to the clock inputs of the first and second JK- triggers, other inputs of the first and second elements AND-NOT are connected respectively to the two first outputs of the decoder, and the inputs of the first and second elements AND-NOT to the corresponding counting inputs of the binary reversible counter Two outputs of which are connected respectively to the first and second inputs of the decoder, the fifth input of which is connected to the output of the network voltage and switching voltage character matching indicator, and the sixth and seventh inputs to the corresponding two outputs of the time relay, first, second and third D their triggers are connected to the corresponding control pulse shapers, and the D inputs are connected to the third, fourth, and fifth outputs of the decoder, respectively, and the C inputs to the outputs of the first and third IL elements, respectively. -NOT inputs of which are connected to the outputs of the respective plate line voltage indicators, the second inputs of AND gates connected to outputs of the sixth and seventh decoder, J-inputs the first v second JK-flip-flops are respectively connected to the outputs of the first and second AND and K inputs

through the first and second inverters to the outputs of the same elements And, the outputs of the first and second JK-flip-flops are designed to be connected to the control circuits of the drive mechanism of the mechanical tap changer of the transformer.

Introduction of a phase-adjustment unit provides phase-by-phase transformer voltage control within the control stage by switching the thyristor switches in each phase, thereby increasing the number of three-phase transformer control stages for a given number of transformer control windings, increasing the voltage control accuracy of the transformer under load by three times.

FIG. 1 shows a functional diagram of the device; in fig. 2 - timing charts with increasing voltage; in fig. 3 - time diagrams with decreasing voltage.

FIG. 2 and 3 are given the following notation:

62 (84) - voltage at the terminals A of the primary winding of the transformer;

63 (85) is the signal from the output of the network voltage and switching voltage character matching indicator, which determines the position of the contacts of the mechanical switch of the transformer taps (O is even, 1 is odd);

64 (86) control signal higher circuit;

65 (87) - control circuit signal Below;

66 (88) - pulses produced by a clock pulse generator;

67 (89) - output signal Q1 of the decoder;

68 (90) - output signal Q2 decoder;

69 (91) - signal at the forward counting input of the counter;

70 (92) - signal on the reverse counting input of the counter;

71 (93) - low-order signal at the output of the counter;

72 (94) th high-order signal at the output of the counter;

73 (95) - output signal Q3 of the decoder;

74 (96) - output signal Q4 decoder;

75 (97) - signal output Q5 decoder;

76 (98) - output signal Q6 decoder;

77 (99) - output signal Q7 of the decoder;

78 (100) - JK-trigger output signal; 79 (101) - JK-trigger output signal;

80 (102) is the signal corresponding to the positive half-wave of the mains supply voltage;

81 (103) —a signal corresponding to a negative half-wave of the mains voltage of phase A at the output of the indicator of the sign of the mains voltage;

82 (104) - control pulse synchronization signal at the element output

5 synchronization of control pulses at the output of the element OR NOT;

83 (105) - synchronized control signal for the thyristor key of the alternating current of phase A at the direct output of the D-flip switch.

The device contains thyristor keys 1 and 2 of alternating current, with clips 3 and 4, which by means of movable contacts 5 and 6 of a mechanical switch with

5 by an electromechanical drive 7 can be connected to any two adjacent branches X1 ... XN of the adjustable winding 8 of the transformer, the current limiting reactor 9, with its extreme leads

0 connected to the input ends of the thyristor switches 1 and 2, and the middle output excluded to the mains supply, drivers 10 and 11 of the control pulses of the thyristor keys.

These elements constitute the power unit 12 of one of the phases of the device, connected to the terminals 13 and 14 of the mains supply.

The two other phases of the device have the same power units 15 and 16, connected respectively to terminals 17, 18 and 19, 20 of the mains.

The power blocks can be connected with their leads either according to scheme Y or scheme D, depending on how the windings 8 of the transformer are to be connected.

5K power supply terminals of all three phases

indicators 21–23 of the network voltage are connected by their inputs.

To terminals 3 and 4 of the power unit 12 is connected by its inputs indicator 24

0 signs commuting voltage.

Indicators 21-24 are converters of alternating sinusoidal voltage into rectangular pulses of one polarity, and rectangular pulses of one of the indicator outputs correspond to the positive half-waves of the sinusoidal input voltage, and on the other to negative half-waves.

.

The outputs of the indicators 21 and 24 are connected to the inputs of the indicator 25 of the coincidence of the signs of the network voltage and the switching voltage. Indicator 25 of the coincidence of the network and switching voltage symbols is a phase comparator.

The phase control unit 26 has input and output circuits 27-43, and also includes a generator of 44 clock pulses, two two-input elements AND-HE 45 and 46, a binary reversible counter 47, a decoder 48, a time relay 49, three two-input elements IL AND -NOT 50-52, three D-flip-flops 53-55, two two-input elements And 56 and 57, two inverters 58 and 59, two JK-flip-flops 60 and 61.

The pulse generator 44 is a multivibrator with a large duty cycle of the output pulses, the frequency of which is chosen from the conditions of the speed of transformer voltage control and must be fr so 2 T. net.

Two elements AND-NOT 45 and 46 are connected by two of their inputs to the generator output 44 clock pulses, and two of their outputs to the forward and reverse counting inputs of a binary reversing counter 47, respectively, the outputs of the lower and higher bits of which are connected to the inputs A1, A2 of the decoder 48, and the inputs are A3. A4 is connected to circuits 27,28 of the control Higher, Lower, input A5 - with the outputs of the indicator 25 coincidence signs of the network voltage and the switching voltage, inputs A6, A7 of the decoder 48 are connected to the outputs of the time relay 49, the installation inputs of which are connected to the chains Manage Above, Below. The outputs of the decoder 48 are connected; 01-with the second input element AND-45; 02-s.second input element AND-HE 46; Q3, Q4, Q5- with D-inputs of D-flip-flops 53-55, respectively; Q6-C input element And 56; Q7- with the input element And 57. D-flip-flops 53-55 are sinhrinizirovanny on inputs C from the outputs of the elements IL AND-NES 50-52, the inputs of which are connected to the outputs of the indicators 21-23 sign network voltage respectively. The direct outputs of the D-flip-flops are connected to the inputs of the shapers of control pulses of the thyristor switches of the even taps of a mechanical switch, and the inverse outputs of the D-flip-flops are connected with the shapers of the control pulses of the thyristor switches of the odd taps of the respective phases.

The second inputs of elements And 56 and 57 are connected to the control circuits Above, Below, and the outputs of elements 56 and 57 are connected to the J-inputs and through inverters 58 and 59 - with

K-inputs JK-flip-flops 60 and 61, which are synchronized to the inputs C from the generator output 44 clock pulses. The outputs of the JK-flip-flops 60 and 61 are connected to the control circuit of an electromechanical actuator

0 7.

The device works as follows.

Let the mechanical switch of the transformer taps be in a position in which the thyristor switch 1 is connected through the movable mechanical contacts of the switch to the tap of the winding 8 corresponding to a greater number of turns than the branch to which

0 thyristor key 2. In this position, the mechanical phase switch of the rectangular pulses of the outputs of the indicators 21 and 24 of the network voltage and the switching voltage will be the same, and the output

5 of the indicator 25, the coincidence of the signs of the network voltage and the switching voltage will be a high logical level corresponding to the logical unit (1). Such a position will be called odd. When moving to the next position of the mechanical switch, a thyristor switch 2 will be connected to the outlet corresponding to a large number of turns of the winding 8. Signals at the indicator outputs 21

5 characters of the network voltage and the indicator 24 characters of the switching voltage will be in antiphase, and at the output of the indicator 25, the coincidence of the characters of the network voltage and the switching voltage will be low

0 voltage level corresponding to logical zero (O). This position will be called even.

FIG. 1 shows the odd position of a mechanical switch, with

By this, the logical unit enters the A5 input of the decoder 48. At the time ti in the control circuit 27, the logical unit level is set above. At the output 01 of the decoder 48 is set (in

0 according to the truth table) level 1, allowing the passage of clock pulses from the output of the generator 44 to the forward counting input of the binary reversing counter 47 through the element IS-NOT 45.

5 Starting from this moment, along the leading edges of the inverted clock signal generator, the information at the outputs of the counter 47 will vary in binary code. At time t2 (fig. 2) - 01, t4 - 11..

When appearing on both outputs of the counter 47, level 1, on outputs 01 and 02, levels O are set, which prohibits the passage of clock pulses to the counting inputs of the counter and prohibits further counting in the forward direction. Information from the outputs of the counter 47, which is fed to the inputs A1, A2 of the decoder 48, is converted from the binary code into the control signals of the three phase thyristor switches and supplied from the outputs of the decoder Q3, Q4, Q5 to the D inputs of the D-flip-flops 53-55, which synchronize control pulses on signals coming from the outputs of the elements OR NOT 50-52. The acquisition of a synchronized control pulse by a thyristor switch 2 of phase A is shown in diagrams 80-83 (Fig. 2). The control pulse of the thyristor key 1 is the inverse of the control pulse of the thyristor key 2. At time ts (Fig. 2), the thyristor switches of phase A switch, key 2 opens, and the voltage on the transformer rectifying load increases. The switching times of the control pulses of phases B and C are not shown in the diagrams, they are produced according to the clock pulses generated by the signals of the indicators 22 and 23 of the sign of the mains voltage, respectively. As can be seen from the diagrams (Fig. 2 and 3) and the truth table of the decoder 48, the arrival of clock pulses to the counting inputs of counter 47 is carried out only if there is a level of a logical unit or in circuit 27 Above or in circuit 28 Below, Split Level 1 with the level O in the control circuits Above, Below, it is possible to set any code from 00 to 11 at the output of the counter 47, and therefore, within one step of winding 8 on the transformer rectifying load - three voltage levels, which gives opportunity to increase the accuracy of the adjustment Rectifier load three times.

With steady code 11 at the output of the counter 47, the odd position of the contacts of the mechanical switch of the transformer taps, a high logic level in the control circuit. Above the output of the And 56 element, at the J input of the JK flip-flop 60 is set the level 1, and at the K input of that the same trigger for it is the inverse level O, and on the leading edge of the clock pulse arriving at the C input of the trigger (time te, diagram 78, fig. 2), at its output a logical unit corresponding to the command for switching the drive mechanism 7 of the mechanical toggle ate towards increasing voltage. The drive switches the contacts of the mechanical switch. With the arrival of the contacts in the new fixed position at the output of the indicator 25, O is established, which corresponds to the even position of the contacts of the mechanical switch. FIG. 2, moment t corresponds to the opening of the odd contacts of the mechanical switch, ts to the closing of the odd contacts in the new fixed position of the switch. At time ts, the signal at the output of the indicator 25 changes, output 06 of the decoder 49 is set to O, which prohibits the command to the drive mechanism, and with the arrival of a clock pulse at the output of the JK flip-flop 60, the logic zero level is set.

Provided that in the control circuit of Higher-level 1, the voltage is further regulated (increased), but the logical unit level is not set at output Q1, but output Q2 of the decoder 48, and the clock pulses are fed to the reverse count input 47 (Diagram 70), the code at the output of the counter decreases with the frequency of the clock pulses, which ultimately leads to turning off the thyristor switches 2 and turning on the thyristor switches 1, which provide a higher switch in the even position of the mechanical switch contacts Level of voltage to the rectifier load transformer.

The voltage regulation for the lowering is performed in the reverse order when applying to the control circuit 28 Below the level of the logical unit.

Since the phase transformer operates in an asymmetrical mode, in order to equalize the load between the phases in time and eliminate overheating of the windings of any phase, a time relay 48 is inserted in the device, which is set to zero position at level 1 in any of the control circuits. or below. If in both control circuits the levels are O, then the information on the outputs of the time relay 49 is changed by the binary code 00, 01, 10, 00, 01, etc. at intervals of time depending on the operating conditions of the transformer.

In this case, the information at the outputs Q3, Q4, Q5 of the decoder 48 is cyclically shifted (table).

Changing the code at the outputs A6, A7 of the decoder 48 does not affect the change of signals of the other outputs of the decoder: Q1 is the resolution of the passage of clock pulses to the direct counting input of the counter 47; Q2 - on the reverse; Q6, Q7 is the resolution of supplying control pulses to the drive mechanism 7 of the mechanical switch of the transformer windings taps.

The total voltage control range is determined by the number of branches of the adjustable transformer winding, and the accuracy is -1/3 of the voltage level.

The proposed device makes it possible to regulate the voltage within one step of the adjustable winding, i.e. allows you to increase the number of stages of regulation by three times with a given number of tapping of an adjustable winding and, therefore, to improve the accuracy of voltage regulation on the load three times with the minimum number of thyristor switches.

Claims (1)

The invention The device for controlling an adjustable AC-to-AC converter with a mechanical switch of transformer windings taps, containing thyristor control pulse drivers, indicators of the sign of the network voltage and the switching voltage by the number of phases with positive and negative signs, indicator of coincidence signs on network voltage and switching voltage of a single phase, which is different from the fact that, in order to increase the control accuracy, it is equipped with a power supply unit o-phase control, including a clock generator, the first and second two-input elements of NAND, a binary reversible counter, a decoder with seven inputs and seven outputs, realizing the matching of the output with the input signals in accordance with the truth table, the time relay, the first, the second and third two-input elements OR- NOT, the first, second and third D-triggers, the first and second two-input elements And, the first and second inverters, the first and second JK-flip-flops, the third and fourth inputs of the decoder are designed for supplying signals to them Above, Below and connected respectively to the first inputs of the first and second two-input elements AND, as well as to the first and second setting inputs of a time relay; the output of the clock generator is connected to the first inputs of the first and second two-input elements AND-NOT and to the synchronizing the inputs of the first and second J K-flip-flops, the other inputs of the first and second elements AND-NOT are connected respectively to the two first outputs of the decoder, and the inputs of the first and second elements AND-NOT to the corresponding counting inputs voichnogo down counter, whose two outputs are connected respectively to first and second inputs of the decoder, a fifth input connected to the output of the coincidence of the indicator marks the mains voltage and switching voltage, and the sixth and seventh inputs - to the corresponding two outputs of the time relay, the first, second and third D-flip-flop outputs are connected to the corresponding control formers of the impulses, and the D-inputs are respectively the third, fourth, and fifth outputs of the decoder, C-inputs, respectively, with the outputs of the first and third OR-NOT elements, whose inputs are connected to the outputs of the corresponding indicators of the sign mains voltage, the second inputs of the elements And are connected to the sixth and seventh outputs of the decoder, the J-inputs of the first and second JK-flip-flops are connected respectively to the outputs of the first and second elements And, and the K-inputs through the first and second inverters - to the outputs of the same elements And, the outputs of the first and second J K-flip-flops are designed to connect to the control circuits of the drive mechanism of a mechanical tap of the transformer windings. X - any state # ate -&eight thirty l If  G1-J-C J. io. JIHL I LZL: en VLo   i 1CS L .ЛЦЛD0: Ц Л-Г  ll Ј / J rt 5 (4, 7 Fm.z t l gg (