SU1739316A1 - Signal integral parameters sensor - Google Patents

Abstract

The invention relates to an information-measuring technique and can be used to convert an electrical signal into a constant voltage proportional to its quasi-peak, root-mean-square value, as well as the shape factor. The transmitter contains five switches 1, 2, 3, 4, 5, quad 6, differential integrator 7, sampling-storage units 8, 15, reference voltage source 9, module driver 10, clock generator 11, pulse drivers 12, 18 , multiplication unit 13, conversion unit 14 and analog voltage divider 16. 1 hp f-ly, 2 ill. sl C

Description

Xi cj o

with a

The invention relates to an information-measuring technique and is intended to measure quasi-peak, rms values of signals, as well as shape factors (form factors).

The known circuit of the form factor meter contains two measuring transducers, one of which converts the measured alternating voltage into a constant proportional to the average measured value, the other into a constant, proportional to the mean square value of the measured. The voltages from the transducer outputs go to the coils of the logometer, the scale of which is calibrated in units of the form factor.

The accuracy of the conversion in this device, built on an open circuit with simultaneous conversion of the signal in two independent channels, is limited by the errors of the elements included in it. In addition to low accuracy, the device does not provide work in automatic mode.

The known circuit of the measuring converter of the integral characteristics of the waveform, comprising four switches, a peak detector, a multiplier, a quad, a differential integrator, a sampling and storage unit, a pulse driver, a voltage source, a module driver, a clock generator, the second fixed contact of the first switch connected with the first input of the converter, the switching contact of the first switch is connected to the input of the peak detector, the output of which is connected to the first in ohm multiplication unit, the output of the latter is connected to the input of the quad and the first fixed contact of the fourth switch, the second fixed contact of which is connected to the output of the quad, the switching contact of the fourth switch is connected to the switching contact of the second switch, two fixed contacts of which are connected to two corresponding inputs of the differential integrator, the output which is connected to the input of the sampling and storage unit, the output of the latter is the output of the converter and is connected to With the fixed contact of the first switch, the first fixed contact of the third switch is connected to the second input of the converter, the second fixed contact to the output of the reference voltage source, and the switching contact to the input of the module former, the output of which is connected to the second input of the multiplication unit, the control inputs of the first, second and third switches and input

the pulse driver is connected to the output of the clock generator, and the pulse driver output is connected to the control input of the sampling and storage unit.

In each of the two modes, said converter allows for the conversion of input signals into a voltage proportional to the amplitude coefficients and

averaging. The transition from mode to mode is manual. In this case, the systematic errors of the blocks included in the converter are corrected and do not have a practical effect on the result of the conversion.

However, this device does not provide the possibility of measuring the quasi-peak and root-mean-square values of the signals, as well as the form factors (form factor), moreover, it does not allow the automatic change of operating modes.

The aim of the invention is to expand the functionality.

This goal is achieved by the introduction of five new elements and the organization of a number of new links. Into a device containing four switches, a multiplication unit,

a quad, a differential integrator, a first sampling and storage unit, a reference voltage source, a module driver, a clock generator, and a first pulse generator, where the second

the fixed contact of the first switch is connected to the first input of the converter, the output of the multiplication unit is connected to the input of the quad, the switching contact of the fourth switch is connected to

the switching contact of the second, fixed contacts of the latter is connected to two inputs of the integrator, the output of which is connected to the input of the first sampling unit and storage, the output of which is connected to the first fixed contact of the first switch, the first fixed contact of the third switch is connected to the second input of the converter, the second fixed contact of the third switch connected to the output of the reference voltage source; the switching contact of the third switch is connected to the input of the module former; output the latter is connected to the second input of the multiplication unit, the control inputs of the first and second

the switches and the input of the first pulse generator are connected to the output of the clock generator, and the output of the first pulse driver is connected to the control input of the first sampling and storage unit, a fifth switch, a second pulse driver, a second sampling and storage unit, an analog voltage divider and a counting unit, the input of the counting unit is connected to the output of the clock generator, and the output is connected to the control inputs of the third, fourth and fifth switches and the input of the second pulse generator , the output of the latter is connected to the control input of the second sampling and storage unit, the input of which is connected to the output of the first sampling and storage unit, as well as to the fixed contact of the fifth switch and the first input of the analog voltage divider, the output of the second sampling unit and storage is connected to the third output of the converter and the second input of the analog voltage divider, the output of which is connected to the first output of the converter, the switching contact of the fifth switch is connected to the second output of the converter, the switch ayuschy first switch contact is coupled to the first input of the multiplication unit, whose output is connected to a first fixed contact of the fourth switch, the second fixed contact is connected to the output of the squarer.

Figure 1 shows the structural diagram of the proposed Converter; FIG. 2 is a block diagram of a conversion unit.

The converter contains switches 1-5, quadrant b, differential integrator 7, block 8 and 15 of sampling and storage, reference voltage source 9, driver 1 module, clock generator 11, pulse drivers 12 and 18, multiplication unit 13, scaling unit 14 and an analog divider of 16 voltages.

The switch 1 performs a sequential switching to the first input of the block 13 multiplying the feedback signal from the output of the first block 8 of the sample and storage and the input signal from the first input of the converter. Switch 3 makes alternate connections to the input of shaper 1 of the input signal module from the second input of the converter and the output of the source 9 of the reference voltage. The output signal from the imaging unit 10 is supplied to the second input of the multiplication unit 13, the output of which is connected to the input of quad B and the first fixed contact of switch 4, the second fixed contact of which is connected to the output of quad. 6. The switching contact of switch 4 is connected to the switching contact of switch 2, fixed contacts which is connected to the corresponding inputs of the differential integrator 7, the output of the latter is connected to the input of the first block 8 of the sample and storage, the output of which is connected to the input of the second sampling unit 15 and the storage, the fixed contact of the switch 5 and the first input of analog divider 16 voltages, the second input of which is connected to the output of the second block 15 and sample and hold third output transducer. The output of the analog divider of 16 voltages is connected to the first output of the converter, and the switching contact of the switch 5 is connected to the second output of the converter. The control inputs of switches 1 and 2 and the inputs of the scaler 14 and the first pulse generator 12 are connected to the output of the clock generator 11. The output of the first pulse generator 12 is connected to the control input of the first sampling and storage unit 8, and the output of the counting unit 14 is by control inputs switches 3-5 and the input of the second pulse generator 18, the output of which is connected to the control input of the second sampling and storage unit 15.

The scaling block contains a counter 19 on an arbitrary basis, for example, with an additional extension code, recalculation trigger 20, a two-input element IS-HE 21 and an inverter 17, and the preset inputs of the counter can be loaded from the handheld console or from a microprocessor, counting the input of the counter 19 and the input of the inverter 17 are connected to the output of the clock generator 11, and the transfer output of the counter - with the counting input of the conversion trigger 20, the inverse output of which is connected to one of the inputs of the element EH 21, to the other input of which The pulses from the output of the inverter 17, the output element AND-NOT is the output of the counting unit.

For convenience, the order of operation of the converter is called the position of the switches, in which the switching contact is closed with the first fixed contact, the upper or initial position, and when with the second fixed contact, the lower position.

When measuring the integral characteristics of a single signal, it goes to both inputs of the converter. Next, the Converter operates as follows.

Before starting work on the parallel loading path, the conversion unit 14 is loaded with an addition code of the required number of clock cycles, which is automatically rewritten during operation.

Quasi-peak measurement mode.

In the first cycle, the switches 1-4 are moved to the lower position. In this case, the switch 1 connects the input voltage U (t) to the first input of the multiplier 13, the switch 3 connects the output of the source 9 of the voltage reference Uon to the input of the module 10 and then to the second input of the multiplication unit 13. At the output of the latter, a voltage appears

UMyi U (t) Uon (1)

which enters the input of the quadrant 6. At the output of the latter, a voltage is formed

(t) (2)

This voltage through the switches 4 and 2 is supplied to one of the inputs of the differential integrator 7 (suppose, on). The incoming voltage is integrated for the duration of the pulse of the clock generator 11, and the voltage at the output of the integrator 7 becomes

III i / U (t) dt

(3)

where t is the time constant of the differential integrator 7;

T is the pulse duration of the clock generator 11.

As the clock decays, the circuits of the formers 12 and 18 pulses emit short pulses to the control inputs of blocks 8 and 15 of the sample and hold and record the voltage from the output of the differential integrator 7.

In the second cycle (in the pause between the pulses of the clock generator), the switches 1-4 are in the initial position (upper). Switch 1 connects to the first input of block 13 multiplying the voltage from the output of block 8 for sampling and storage, switch 3 connects to the input of the former module 10 a voltage supplied to the second input of the converter (in the considered case U (t). At the output of block 13 multiplying by is voltage

UMy2 UMl | U (t) |, (4)

which through switches 4 and 2 is fed to the second input of the integrator 7 (input -).

The incoming voltage is integrated for the time T, as a result of which the output voltage of the differential integrator 7 at the end of the second cycle is equal to

UM2 / (t) - UMJ U (t) |}. dt. (5) about

In the third cycle, the actions performed in the first cycle are repeated. As a result, the output voltage of the differential integrator 7

Tt

iiz -1 / U (t) dt - f uJu (t | dt,

oo

(6)

The following procedure can be continued an unlimited number of times. In this case, the nth output voltage of the differential integrator 7 is determined from the expression

| / U (t) if Uni | U (t) | dt, oo

(7)

Taking into account that in each integration cycle the values of Uon and UMn are constant, we obtain

ui and

 op

| / U2 (t) dt

 about

T / iU (t) fdt

1 n

(eight)

0

five

0

five

From (8) it follows that Dun is an estimate of the quasi-peak value of the signal. In this case, as well as in the known device, the systematic errors of the blocks used are corrected, and the accuracy is limited almost only by the accuracy of the source 9 of the reference voltage. The quasi-peak values of the signals arrive at the output 3 of the converter and simultaneously to the second input of the analog divider 16 voltages.

RMS measurement mode.

After a predetermined number of cycles has been completed, the calculating unit 14 blocks the passage of pulses from the clock generator 11 and generates a high level signal at its output. In this case, switches 3-5 are transferred to the lower position and remain there until the end of the current measurement cycle (the number of ticks in this cycle is the same as in the previous one).

In the first cycle, switches 1 and 2 are moved to the lower position. By analogy with the previous mode, the voltage at the output of block 13 multiplying is

UMyi U (t) Won. (9)

This voltage is fed to the input of the quad 6, the output of which is the voltage

(t) Wonf (S)

Further, through switches 4 and 2, it goes to one of the inputs of the differential integrator 7 (suppose, to input +). The incoming voltage is integrated for the duration of the pulse of the clock generator 11, and the voltage at the output of the integrator 7 becomes equal to

11 and 1 | / U (t) wonf dt (11)

about

The voltage (11) according to the signal of the pulse driver 12 is rewritten into block 8 of sampling and storage.

In the second cycle, the switches 1 and 2 return to the initial state and a voltage appears at the output of the multiplication unit 13

UMy2 UMlUon, (12)

which enters the input of the quadrant 6. At the output of the latter appears the voltage

UKB2 (11i1 Uon) 2, (13)

which, via switches 4 and 2, goes to the second input () of the differential integrator 7. At the end of the second cycle (after time T), the output voltage of the differential integrator 7 is equal to

UM2 | / (t) Wonf- (UMiUon)} dt.

(14)

In the third cycle, the actions performed in the first cycle are repeated. As a result, the output voltage of the differential integrator 7

ui3 | / UMUon 2 dt-j} -

(UniUon) 2 dt, (15)

The output voltage of the integrator 7 after n cycles is determined from the expression

tt

i / U (t) Wonf dt / (UnnUon) 2 dt.

oo

(sixteen)

From (16), taking into account the comments made for the previous regime, we obtain

 U2 (t) dt

(17)

0

five

0

j.

five

0

0

five

As follows from (17), 11ip is an estimate of the root-mean-square value of the signal U (t), while along with the systematic errors of the blocks used, the influence of the source 9 of the reference voltage on the conversion accuracy is eliminated. The rms values of the signals U (t) through the switch 5 are fed to the second output of the converter and simultaneously to the first input of the analog divider 16 voltages.

Mode of measurement of form factors (form factor).

The execution of the mode of measurement of the form factor, determined from the expression

Cf (, 8)

where UKn is the quasi-peak value of the signal U (t);

UCK - rms value of the U (t) seknal,

starts simultaneously with the measurement mode of the rms value of the signal U (t). By this time, at one of the inputs of the analog divider of 16 voltages, there is a divisible ip value. As the iterative procedure of forming the value of the divider UCK arriving at the second input of the analog divider of 16 voltages, the result of dividing more and more approaches the desired value Kf. After p-clock measurements of UCK, the output signal of the analog voltage divider 16 is an estimate of the shape factor Kf of the signal U (t). In addition to the noted integral characteristics (ICP,). The proposed converter allows measuring functionals of a more general form. So, when the signal Ui (t) is fed to the first input, and the signal Ua (t) to the second input, based on (8), (17), (18), we get: for the first mode

one

Y / U2 (t) dt

 , 09)

Y / IU2 (t) ldt

for the second mode

 Ui2 (t) dt, o

for the third mode

(20)

i} tf (t) dt

 about

1 / IU2 (t) ldt

 (21)

T

It is known that in the manufacture of integrated circuits it is necessary to control the current noise of the resistors of both semiconductor and thin-film technology. The noise characteristic of resistors is used to characterize the noise of resistors. According to GOST, the noise factor of the resistors Km is measured as the ratio of the rms value of the voltage of the current to the voltage of the constant voltage U- applied to the resistor.

Currently, there are no devices that allow the measurement of Ks in the automatic mode. In this connection, it is of practical interest to use the proposed converter in the Ksh measurement problem. So, when connecting to the first input voltage of the current noise Um of the test resistor, and to the second input - the constant voltage U- supplied to it, on the basis of (8), (17) and (18) in the third mode, we obtain the desired estimate

Ji / UJLdt

I ,, 24 Oh

ip wap

(22)

It is obvious that in all the considered modes, the use of iterative correction of systematic errors of the blocks provides the proposed converter with high conversion accuracy. The functionality of the proposed converter is greatly expanded (three new modes of operation have been obtained) by the introduction of switch 5, conversion unit 14, second sampling and storage unit 15, second pulse generator 18 and analog voltage divider 16. To measure periodic signals in the frequency range, the clock generator circuit 11 provides for the possibility of varying the duration and duration of the pulse.

Claims (2)

Claims 1. A measuring transducer of integral characteristics of signals comprising four switches, a multiplication unit, a quad, a differential integrator, the first sampling unit and storage, the reference voltage source, the module driver, the clock generator and the first pulse driver, while the second fixed contact of the first the switch is connected to the first input of the converter, the output of the multiplication unit is connected to the input of the quad, the switching contact of the fourth switch is connected to the switching contact the second, fixed contacts of the latter are connected to two inputs of the integrator, the output of which is connected to the input of the first sampling and storage unit, the output of which is connected to the first fixed contact of the first switch, the first fixed contact of the third switch is connected to the second input of the converter, the second fixed contact of the third switch is connected to the output of the reference voltage source, the switching contact of the third switch is connected to the input of the generator module, the output of which is connected to the second th input multiplying unit control inputs of the first and second switches and the first input of the pulse shaper connected to the output of the clock generator, and a first pulse shaper output is connected to a control input of the first block Sampling and storage, characterized in that, in order to expand the functionality, a fifth switch, a second pulse shaper, a second sampling and storage unit are introduced into it, a voltage divider and a conversion unit, the latter input being connected to the clock generator output, and the output to the control inputs of the third, fourth and fifth switches and the input of the second pulse generator, the output of the latter is connected to the control input of the second sampling and storage unit, whose input is connected to the output of the first sampling and storage unit, as well as to the fixed contact of the fifth switch and the first input of the voltage divider, the output of the second sampling and storage unit is connected to the third output of the converter, and with the second INPUT a voltage divider, the output of which is connected to the first output contact switch The switch is connected to the second converter output switching the contact of the first switch is connected to the first input of the multiplication unit, the output of which is connected to the first fixed contact of the fourth switch, the second fixed contact of which is connected to the output of the quad. 2. The converter according to claim 1, that is, that the counting unit contains a counter on an arbitrary basis, for example, with the loading of a supplement code, a counting trigger, a two-input AND NAND element and an inverter, counting the counter input and the inverter input are connected to the clock generator output, and the counter transfer output is connected to the counting trigger input, the inverse output of which is connected to one of the inputs of the NAND element, to the other input of which the pulses come from the inverter output, the output of the NAND element is the output of the scaler but. in the output of t g (11) 2K code Set 1 Exit 21 2Q Q FIG. 2