SU1721632A1 - Bidirectional shift register - Google Patents

Abstract

The invention relates to digital computing, and more specifically to registers, and can be used in discrete automation devices on potential logic elements in an integrated design. The aim of the invention is to improve the reliability of the shift register. This goal is achieved by the fact that each memory cell of the shift register contains the seventh 1, eighth 10, ninth 5 and tenth 7 AND-NOT elements with corresponding links. Triggers formed by the listed IS-NOT elements prohibit overwriting information in the register cells until the sync signal arrives at the inputs of all cells. As a result, the performance of the register does not depend on the structural and technological features of the crystal, the topology of the synchronization circuits, and the method of buffering the clock signal. 5 il. fe

Description

The invention relates to digital computing, and more specifically to registers, and can be used in discrete automation devices on potential logic elements in an integrated design.

When designing custom and semi-custom LSIs and VLSIs, the problem arises of eliminating concurrent signals arising in synchronization chains under the influence of constructive-technological and topological factors. This problem can be solved by creating functionally reliable devices that are part of an LSI and VLSI, in particular, shift registers, whose performance would not depend either on the length of the interconnects or on the technological features of the crystal.

A shift register is known that is implemented on the basis of a Webb trigger and is free of C contests.

The disadvantage of this register is the heterogeneity of the memory cells and the large number of interconnects, which complicates the design process of multi-bit shift registers. In addition, this register is not reversible. The use of the C-status suppression principle applied in this register when building a reverse shift register leads to an even greater increase in the number of inter-bit links.

The disadvantage of this register is also the dependence of its functional reliability on the specific trace of synchronization circuits. Due to the different delays of the shift sync signal in the communication lines,

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synchronizing the output of the sync source with the sync inputs of the memory cells of the register, it is skewed, as a result of which the fronts of the sync signal at the inputs of the memory cells will not occur simultaneously, which may cause the register to malfunction.

Also known is a reversing shift register with duplication of the gaps of the formation of interdigit information. His scheme is optimal in terms of the number of equipment used in it and the number of interdisciplinary connections.

However, this register functions reliably only when the positive edges of the sync signal are dephased. In the case of skewing of negative fronts, malfunctions in the register are possible,

The closest in technical essence to the present invention is a shift register constructed on single-type memory cells and having a relatively small number of inter-bit links.

However, the known register shifts information in one direction only. The known register is reliable, but it cannot be used as a reverse register, since attempts to convert it by known methods to reverse degrade its reliability.

The purpose of the invention is to increase the reliability of the register.

A shift register containing memory cells, each of which consists of six AND-NOT elements, with the first input of the first AND-NO element connected to the output of the second AND-NO element, the first input of which is connected to the output of the first AND-NE element and the first the input of the third element AND-NOT, the second input of which is connected to the second input of the second element AND-NOT and the output of the fourth element AND-NOT, the first input of which is connected to the output of the third element AND-NOT, and the second input is connected to the third input of the second element AND- NOT and connected to the register clock bus , the second input of the first NAND element of each memory cell, except the first one, is connected to the output of the fifth NAND element of the previous cell, and the second input of the first NAND element of the first memory cell is the first information input of the register, the output of the fifth the AND-NOT element of the last memory cell is the first information output of the register, the seventh, eighth, ninth and tenth elements of the AND-NOT are additionally entered, the first input of the seventh AND-NOT element is connected to the first input of the first AND-NOT element, the first the input of the eighth element and NOT

the first input of the ninth NAND element, the second input of which is connected to the output of the tenth NAND element and the first input of the sixth NAND element, the output and second 5 input of which are connected respectively to the first input and output of the fifth NAND element, the second input of which is connected to the output of the ninth element NAND and the first input of the tenth element NAND, the second

0 whose input is connected to the output of the fourth element AND-E E and the second input of the eighth element AND-NOT, the output of the seventh element AND-NOT connected to the fourth input of the second element AND-NOT and the third input of the third element AND-NOT, and the second input of the seventh AND-NOT element is connected to the left shift register bus, the third input of the first AND element is NOT connected to the right shift register bus, the output of the fifth AND element is NOT

0 of each register memory cell, except the first one, is connected to the third input of the seventh AND-N element of the previous memory cell, and the output of the first AND-N element of the first cell is the second information output of the register; the third input of the seventh AND-NIGHT last element the memory cell is the second information input of the register, the output of the eighth AND-NOT element of each memory cell, except the first and last, is connected to the third inputs of the ninth and tenth AND elements of the previous memory cell and the fourth inputs of the ninth and the tenth element and - NOT a subsequent memory cell, exits

The 5 eighth AND-NOT elements of the first and last memory cells are the first and second register clock confirmation outputs, respectively, and are connected to the fourth inputs of the ninth and tenth

0 elements AND-NOT and with the third inputs of the ninth and tenth elements AND-NOT of the second and the penultimate register memory cells, respectively, the third inputs of the ninth and tenth elements of AND-NOT the last cell

The five memories are combined and are the first input of the register clock signal, the fourth inputs of the ninth and tenth elements of the NAND of the first memory cell are combined and are the second input of the confirmation of the register clock signal.

By introducing into each memory cell the register of four additional AND-NOT elements with communication, the recording of new information into each memory cell when

5, the shift is provided only after memorizing the relevant information on the auxiliary triggers of the neighboring memory cells. Availability of additional first and second clock confirmation inputs, as well as first and second outputs

Confirmation of the clock signal makes it possible to build reversible shift registers of virtually any size, which function reliably during the de-scaling of the synchronization signal.

FIG. Figure 1 shows a reversing shift register circuit consisting of identical memory cells (the left memory cell is the first); in fig. 2–4 timing diagrams of the 3-bit shift register for various types of skew clock offsets.

Each memory cell contains a main trigger formed by gates 9 and 10, an additional trigger (gates 5 and 6), a shift-clock confirmation gate 8, a first auxiliary trigger (gates 4 and 3) and a second auxiliary trigger formed by either gates 1 and 2 when shifting to the right (,), or with gates 7 and 2 when shifting to the left (, 11 G).

The shift register has the following conclusions: 11 and 12 - mutually exclusive inputs of the control of the register reverse (when, a shift is made to the right in the direction of memory cells with large numbers; when, a shift to the left is carried out in the direction of memory cells with smaller numbers); 13 (s) - clock input; 14 (D1) - information input of the register when shifted to the right; 15 - information input of the register when shifting to the left; 1 b - information output of the register when shifted to the right; 17 - information output of the register when shifting to the left; 18 and 19 - clock shift confirmation inputs (these inputs are used when organizing shift circuits of random-size registers; for a specific-specific register, these inputs must be supplied with a logic level 1); 20 and 21 are clock-shift confirmation outputs (these outputs are used in organizing shift chains of random-size registers; for a specific-bit register, these outputs are not used).

The shift register works as follows.

At input 13, information is stored in additional triggers 5 and 6 of the register memory cells.

After the positive edge of the shift clock signal (), the auxiliary triggers of each memory cell are set, and the signal of the same polarity is generated at the output of the shift clock confirmation valve 8. This signal gates the main triggers.

9 and 10 adjacent memory cells. Consequently, the main trigger of any memory cell can be set only after the installation of auxiliary triggers of neighboring

the cells. When, when the auxiliary triggers are set, the status of the outputs of the valves 2 and 4, which determine the installation of the main trigger, cannot be changed even with a change in the level at the enabled information input of the cell.

Thus, the main trigger of any memory cell is set in accordance with the data received at the information input of this cell before the positive edge of the clock signal C. The additional triggers are set according to the output states of the corresponding main triggers. After a negative clock edge ()

the information in the main triggers is lost, and the additional triggers store the recorded information until the next clock pulse.

Install the main trigger each

memory cells are possible only after installing auxiliary triggers of neighboring memory cells, which guarantees the correct operation of the register both when shifted to the right and when shifted to the left, regardless of the skew (spin) of the positive edges of the clock signal coming through the chains of the shift to the inputs of the memory cells ti.

Timing diagrams (Figs. 2-4) are for a 3-bit register containing three memory locations.

For all timing waveforms

conventionally denoted by -m, where k is the number of the memory cell valve, am is the number of the memory cell in parentheses are the name

some register outputs), for example, the designation 9-3 (16) represents the output of the ninth gate of the third memory location and is the output of the 16th register.

Conventionally, the delays of all the gates are assumed to be the same, and the delay of switching the valve from the state of logical O to the state of logical 1 is taken equal to the delay of switching the valve from 1 to C - the signal applied to the input of the register shift clock; C-1, C-2, C-3 signals generated from the signal C at the shift 13 chains and actually arriving at the clock inputs of the first, second and third memory cells, respectively.

For all timing diagrams, it is assumed that the inputs 18 and 19 are logic levels 1.

The shift to the right (fig. 2) is carried out at,. In this case, at the exit of the valve 7 of all memory cells there is a level

logical 1, i.e., valves, and are disabled and do not affect the operation of the register.

Let the state of the register before the shift to the right be 100, t, e. The outputs of the memory cells are set as follows:.

It is believed that the input level 14 served logical level O.

When shifting to the right, we will consider the most unfavorable case of dephasing positive edges of the clock signal, when it comes first to the first memory location, then to the second, and finally, to the third.

With both auxiliary triggers, each cell is preset, i.e., the outputs of valves 1 and 3 are in opposite states and depend on the data received at the information input. At the same time, at the outputs of valves 2 and 4 of each memory cell there is a logic level 1, which provides a logic level O at the output of valve 8. This level provides a logic level 1 at the outputs of valves 9 and 10 of the neighboring memory cells. Thus, the information in the main triggers of all memory cells is lost, however the additional trigger (gates 5 and 6) of each cell is in the storage state.

The clock signal of positive polarity () applied to the register () is transformed by the shift chains into signals, and OZ of the same polarity.

Let the signal arrive first at the input of the first memory location. Auxiliary triggers of this cell when set so that the output of the valve 2-1 takes the value of logical O (), and the output of the valve 4-1 takes the value of logical 1 (4-1 1). Logic 1 (8-1 1) is generated at the output of the shift clock acknowledge gate. However, the state of the main trigger of the first cell does not change due to the fact that no logical 1 has yet been formed at the output of the valve, since the auxiliary triggers of the second cell have not yet been established due.

When the outputs of these triggers are set in accordance with D1-2 G: 2-2 T,. Then logical 1 is formed at the output of the valve 8-2, which, together with 19 1, enables the installation of the main trigger of the first cell of the set:, 10-1 0. The outputs of the main trigger establish an additional trigger of the first cell:. Logic 1 at the outlet of the valve and

condition gives permission to install the main trigger of the third cell. However, the installation of auxiliary triggers for this cell has not yet occurred (, 4-3 1), therefore the main trigger of the third cell will be set to an arbitrary state (in the time diagram:,). These outputs will set the auxiliary trigger of the third cell (1).

With the occurrence of a signal, auxiliary triggers of the third cell are set in accordance with the data arriving at the information input from the output of the second cell (the output of the second cell has not changed yet, although the logical clock signal is at its input), t. e. subject to receive, and, as a result. If there is a logic 1 at the valve outputs, the main trigger of the second cell is installed (, 10-2 G). Then an additional trigger for this cell is set (1). The installation of the main trigger of the third cell (9-3 1,) is carried out due to the installation of its auxiliary triggers and coincides in time with the formation. The additional trigger of the third cell is set to (). Thus, after passing the positive edge of the clock signal C, the outputs of the memory cells are set as follows: 5-1 0,

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The state of the register after passing the positive edge of the clock signal 010, which indicates the correctness of the code shifted by one bit to the right to 100, taking into account.

The end of the clock signal C () is transformed by the shift chains into signals,,, of the same polarity.

Let it arrive first at the input of the first cell. The auxiliary triggers of this cell are preset (,,,), the output of the valve takes the logical O value, so that the main trigger of the second cell loses information (9-2 1,). The additional trigger of the second cell is in the storage state.

The signal arriving at the input of the second cell presets its auxiliary triggers (1-2 1, 2-2 1,,). The output of the valve 8-2 takes the value of logical O, which leads to the loss of information by the main triggers of the first (,) and third (,) cells. The additional triggers of these cells are in storage.

Finally, the signal arriving at the input of the third cell presets its auxiliary triggers (,, 4-3-Т,). The output of the valve 8-3 takes the value of logical O.

Thus, after the end of the shift clock signal With a positive polarity, the register stores the code 010.

The shift to the left (Fig. 3) is performed at,. In this case, at the output of the valve 11 of each memory cell there is a logic level 1 and the valves, 1-2, do not affect the operation of the register.

The state of the register before the shift to the left is 110, i.e. the outputs of the memory cells are set as follows:, 5-2 1.. It is believed.

The time diagram (Fig. 3) presents the most unfavorable case of de-phasing of the positive clock fronts for a register with a dynamic input when shifted to the left. The clock signal C comes first to the third cell, then to the second, and finally to the first.

The positive polarity signals C - 3,,, set in series the auxiliary triggers of the memory cells, form at the outputs of the gates 8 a confirmation of the clock signal also positive signals. As the 8-2-T appears, the main and additional triggers are sequentially installed at the beginning of the third cell, then the first cell, and finally the second cell. The main trigger of the first cell is set to an arbitrary state (on the timing diagram:,) and is in this state before the installation of auxiliary triggers of this cell.

The state of the register after a shift to the left by one bit is 101.

The shift of the register contents by one bit to the right and the next one shift to the left to the left are shown in the time diagram (Fig. 4).

The contents of the register to shift (Fig. 4) 011.

Register contents after shifting one bit to the right provided.

The contents of the register after shifting one bit to the left, subject to 010.

For the above (Fig. 4) case of demarcation of the positive edges of the clock signal when shifting to the right, the first and third cells are set first, and then the second. With a shift to the left, with the same characteristics of the shift chains, the first cell is first set, and then the second and third.

As can be seen from the timing diagrams (Fig. 2-4), depending on the skew conditions of the positive edges of the clock signal C in the individual memory cells, it is possible to set the main and additional triggers to an arbitrary state for a short time. The time of the main trigger of this cell in an indefinite state is counted from the time of the installation of this trigger (the presence of a logical 1 at the outputs of the valves 8 adjacent cells) to the time of the installation of auxiliary triggers of this cell. On time diagrams in cases of unspecified installation of the main trigger, the latter was deliberately set to the state opposite to that which it must accept after fulfilling all the conditions of its installation.

The main advantage of the proposed shift register is its functional reliability, which makes it possible to reduce the requirements for the shift clock circuit when designing custom and semi-custom LSI and VLSI.

The proposed scheme allows a different number of stages of clock signal amplifiers for different memory cells. In addition, various communication lengths from clock amplifiers to clock inputs of memory cells are permissible. The proposed circuit functions reliably even when the thresholds of valve actuation vary, whose inputs are the clock inputs of the memory cells.

The proposed register can be implemented on valve arrays, which are based on a multi-input (up to eight inputs) AND gate.

Domestic counterparts of these matrices are basic matrix crystals 1548ХМ1, 1548ХМЗ.

Claims (1)

Invention Form A reversible shift register containing memory cells, each of which contains six NAND elements, the first input of the first NAND element is connected to the output of the second NAND element, the first input of which is connected to the output of the first NAND element and the first the input of the third NAND element, the second input of which is connected to the second input of the second NAND element and the output of the fourth NAND element, the first input of which is connected to the output of the third NAND element, and the second input is connected to the third input of the second AND element -NOT and connected to the register clock bus, the second input of the first AND-NOT element of each memory cell, except the first one, is connected to the output of the fifth AND-NOT element of the previous cell, and the second input of the first AND-NOT element of the first memory cell is the first informational the register input, the output of the last AND memory element of the NAND is the first information output of the register, characterized in that, in order to increase the reliability of the register, each memory cell contains AND AND elements from the seventh to the tenth, the first input of the seventh element is NOT connected to the first the input of the first element AND-NOT, the first input of the eighth element AND-NOT and the first input of the nineth element AND-NOT, the second input of which is connected to the output of the tenth element AND-NOT and the first input of the sixth element AND-NOT, the output and second input of which are connected respectively to the first input and output of the fifth NAND element, the second input of which is connected to the output of the ninth AND – NE element and the first input of the tenth AND – NE element, the second input of which is connected to the output of the fourth AND element NOT and the second input of the eighth element NAND, the output of the seventh element The NAND is connected to the fourth input of the second element NAND and the third input of the third element NAND, and the second input of the 7th element NAND is connected to the left shift register bus, the third input of the first element NID is connected to the shift bus to the right of the register, the output of the fifth AND-NOT element of each register memory cell, except the first one, is connected to the third input of the seventh AND-NOT element of the previous memory cell, and the output of the first AND-NE element of the first cell is the second information the register output, the third input of the seventh element AND-NOT of the last memory cell is the second information input of the register, the output of the eighth element AND-NOT of each memory cell, except the first and last, is connected to the third inputs of the ninth and tenth AND elements previous cell memory and the fourth inputs of the ninth and tenth elements of the IS-NOT subsequent memory cell, the outputs of the eighth elements of the IS-NOT of the first and last memory cells are respectively the first and second outputs of the confirmation of the clock signal of the register and connected to the fourth inputs of the ninth and ten of the same AND-NOT elements and with the third inputs of the ninth and tenth elements of the AND-NOT second and penultimate register memory cells, respectively, the fourth inputs of the ninth and tenth elements of the AND-NOT of the last memory cell are combined and are the first input of register clock signals, the fourth inputs of the ninth and tenth NAND units of the first memory cell are combined and are the second input of the register clock signal. but evj - with FIG. I Phage.}  Ј Ј sb Ј Ј Ј "T T T CQ . 1g "LoIoL" PG-1L „G