SU1721485A1 - Device for measuring mossbauer spectrum - Google Patents

Abstract

This invention relates to Mössbauer spectrometry. The aim of the invention is to improve the accuracy of measurements of the Mössbauer spectrum by eliminating errors in input pulses when switching accumulation channels. Into a device consisting of an I-Krtrigger, two two-input elements And and two buffer counters, an input pulse driver, a pulse clock switch of buffer counters, a third dual input element And, a D-trigger and a logic pulse delay element for switching delay of buffer counters at the time of registration of the current input pulse. 1 il.

Description

The invention relates to nuclear physical research methods and can be used in Mössbauer spectrometers.

The aim of the invention is to improve the accuracy of spectrum measurements by eliminating errors in input pulses when switching buffer counters (accumulation channels).

The drawing shows a block diagram of the proposed device.

The device contains a shaper 1 input pulses, element 2 delay logical pulses, the first 3, second 4 and third 5 logic elements And, shaper 6 clock pulses, IK-trigger 7,

D-flip-flop 8, first 9 and second 10 buffer counters.

The device works as follows.

The pulses that make up the input signal COUNT are shortened in duration by shaper 1 input pulses, which produces pulses of a duration shorter than the minimum, used duration of input pulses COUNT, with the level of logical G at the direct output of the driver and with the level of logical O at the inverse output. From the inverse output of the imager 1 input pulses, the shortened input pulses of the logic level O arrive at the first input of the AND 5 logic element, to

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the second input of which receives the passed shaper 6 clock pulses, the clock pulses of switching of the accumulation channel CHAN logic level 1. The clock pulses of switching of the accumulation channel CHAN are also fed to the count input of the IK flip-flop, which, in response to each received clock pulse, indicates Which of the two buffer counters 9 and 10 should be active (i.e., be in counting mode) at the present time. The signal taken from the direct output of the IK-flip-flop 7 is used as a control for the D-flip-flop 8. The strobe pulse, through which the D-flip-flop 8 goes into the state determined by the logic level at the forward IK output -trigger 7, is the output signal of the logic element 5. The D-flip-flop 8, changes its state in accordance with the I K-flip-flop 7, controls by means of the logic elements And 3 and 4 the flow of the input pulse 1 that passed the former and the element 2 delays of COUNT input pulses, switching it from one buffer counter to other (9 to 10).

The essence of eliminating errors is that in order to avoid cutting the input pulse into parts, the state of the flow control input pulses of D-flip-flop 8 should not change if the input pulse arriving at the second inputs of logic gates And 3 and 4 has already started or (and) not finished yet. This task is solved by introducing an AND 5 logic element, which delays the arrival of the clock pulse of the accumulation channel to the St. Input of the D-flip-flop 8 for the duration of the passage of the input pulse from the inverse output of the driver 1 of the input pulses.

Element 2 of the delay of logical pulses is necessary to compensate for the delay of signal propagation along the circuit. Driver of input pulses 1 - logical element AND 5 - D-flip-flop 8 - inputs of logical elements AND 3 and 4.

The input pulse shaper 1 is needed to shorten the input pulses in order to eliminate the possible situation where the superimposed input pulses merge into one with a duration longer than the duration of the accumulation channel switching pulse, as well as for reliable separation of successive input pulses with the aim increase the stability of the buffer counters 9 and 10,

The clock pulse builder B is designed to standardize accumulation channel switching clock pulses to prevent a situation where the clock pulse arriving at the second input of the AND 5 logic element will be shorter than the input pulse arriving at the first input of the same element.

Experimental verification showed the complete absence of gaps in the counting of input pulses when changing the frequency

following clock pulses for 5 orders at a frequency of input pulses of the order of HMHz.

The proposed device, in comparison with the known, completely eliminates errors (skips) in the input pulses, as well as the cases of recording one input pulse simultaneously into two accumulation channels, failures in the buffer counters caused by the input to the input of buffer counters of non-standard amplitude and pulse duration (truncated input pulses),

Thus, by eliminating

miscalculations, false alarms and failures, the measurement accuracy of the Mössbauer spectra and the calibration distributions of the pulses from the laser interferometer is improved.

Claims (1)

Invention Formula The accumulation device of the Mössbauer spectrum, consisting of an IK-flip-flop, two two-input logic elements And, the second inputs of which are connected, and two buffer counters, while the output of the first logical element And is connected to the counting input of the first buffer counter, the output of the second logic element I is connected to the counting input of the second buffer counter, characterized in that, in order to increase the accuracy of spectrum measurements by eliminating errors of the input pulses when switching the buffer counters, the input pulse generator, the pulse counter generator of the buffer counters, the third the two-input logic element I, the delay element of the logic signal and D-trigger, the direct output of the input pulse generator is connected via the delay element of the logical pulses to the second inputs of the first and second logic element I, and the inverse output of the input pulse generator is connected to the first input of the third logic element And, the input of the clock chip is connected to the clock the input of the IK-flip-flop, the direct output of which is connected to the D-input of the D-flip-flop, the direct output of the clock shaper is connected to the second input of the third logic element I, the output of which is connected to the 5th logical element I. with the clock input of the D-flip-flop, the direct output of the D-flip-flop is connected to the first input of the first logic element And, and the inverse output is connected to the first input of the second