SU1720134A1 - Control gear for single-ended voltage converter - Google Patents

Abstract

The invention relates to electrical engineering and can be used in sources of secondary power supply for electronic equipment and automation devices. The aim of the invention is to simplify the device. A device for controlling a single-voltage DC-DC converter contains a master oscillator 1, an output connected to binary counter 2, the output of which is connected to the S input of RS flip-flop Z. The installation R input of trigger 3 is connected to the output of the element OR 7. Information outputs binary counter 2 is connected to the inputs of the digital-to-analog converter 8. The device also contains a comparator 9, which compares the signal from the output of the digital-to-analog converter 8 and a signal proportional to the supply voltage. The device is equipped with a controlled frequency divider-6 connected to the master oscillator 1. Its parallel load enable input is connected to the RS trigger output 3, and the output is connected to the input of the OR element 7, the second input of which is connected to the comparator output 9. Introduction frequency divider 6 allows to provide pulse width control of the output voltage, as well as to exclude the excess of the volt-second area of the permissible level pulse and the saturation of the output transformer of the converter. 2 Il. sl C

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The invention relates to electrical engineering and can be used in sources of secondary power supply for electronic equipment and automation devices.

A single-ended DC / DC converter is known, comprising a power transistor and a pulse transformer. To control it, you can use a digital device containing a master oscillator, the output of which is connected to the counting input of the first binary counter and the first input of the AND element, the information outputs of the first counter connected to the first inputs of the D / A converter, the first code comparison element, the second code comparison element, and the output Zero settings to the 3 inputs of the first RS flip-flop, the second RS flip-flop and the setup input of the second binary counter; information outputs of which are connected to the second inputs of the first comparison element, outputs of the first and second comparison elements are connected to the inputs of the OR-NOT element, whose output is connected to the R input of the first RS flip-flop, the output of the first RS flip-flop is connected to the base through the preamplifier -emitter junction of the power transistor, the output of the digital-to-analog converter is connected to the first input of the comparator, the second input of which is connected to the terminal of the primary power source through the matching unit, and the output - With the R-input of the second RS-flip-flop, the output of which is connected to the second input of the element And, the output of the element And is connected to the counting subtractive input of the second counter, the second inputs of the first element of the comparison code are connected to the outputs of the setpoint controller. The disadvantage of the device is its complexity.

The purpose of the invention is to simplify the device by achieving a device comprising a master oscillator, the output of which is connected to an input for a binary counter decrement account, the output of which ends a reduction bill is connected to the S input of an RS flip-flop, for which the R input is connected to the output of the OR element, and the output through the preamplifier to the base-emitter junction of the power transistor, the group of information outputs of the binary counter is connected to the group of inputs of the digital-to-analog converter, the output connected to The first input of the analog comparator, the second input of which through the matching unit is connected to the power supply terminal, is additionally introduced a controllable divider.

the frequency at which the input for the reduction account is connected to the output of the generator, the enable input of the parallel load to the output of the RS flip-flop, and the output of the account termination

to reduce - to the first input of the OR element, the first input of which is connected to the output of the comparator.

Figure 1 shows the functional diagram of the device; Fig. 2 shows temporary diagrams for explaining the operation of the device.

A digital device for controlling a single-ended DC-DC converter (Fig. 1) contains a master oscillator, whose output

5 is connected to the inputs of a binary counter 2 decrement counter, the output of which the short count ending is connected to the S input of the RS flip-flop 3, the RS-flip-flop output Z is the device output

0 and through the preamplifier 4 is connected to the base to the emitter junction of the power transistor 5. To the output of the driving oscillator 1 is also connected the counting input for reducing the controlled divider b,

5 parallel load enable input - to the output of the RS flip-flop Z. The end of the count output for reducing the controlled divider 6 is connected to the first input of the element OR 7. Group of information outputs

0 counter 2 is connected to a group of inputs of a digital-to-analog converter 8. an output connected to the first input of an analog comparator 9, the second input of which is connected to

5 terminal 11 of the power source, in addition, the output of the comparator 9 is connected to the second input of the circuit OR 7. The parallel inputs of the controlled frequency divider b are used to supply the control code 12,

0 The device operates as follows.

The master oscillator 1 generates square-shaped pulses (Fig. 2a), the frequency of which is far Shi, where

5 N is the division ratio of binary counter 2; Ti is the inverter conversion frequency.

These pulses are fed to the inputs for counting a binary counter.

0 2 and controlled frequency divider 6, the size of which is chosen so as to provide the necessary frequency of conversion and the necessary error in the formation of the duration of the latitude of the 5th modulated pulse.

At the initial moment of time, at all outputs of counter 2 there is a logical zero signal, RS flip-flop 3 is in the initial zero state, at its direct output there is a logical O,

which allows parallel loading into the controlled divider 6 of the frequency of the control code 12 and through the preamplifier 4, which serves to match the output of the trigger 3 to the input of the transistor 5 and galvanically isolate the signals, closes the transistor 5.

The pulses (Fig. 2a) of the master oscillator 1 cause a change in the state of the counter 2, which leads to a corresponding change in the signals at its information outputs. When the state of the counter 2 corresponds to the reduction counting end, the pulse at the corresponding output (fig.2b), which, acting on the trigger 3, sets it to the unit state (figv) via the S input. This corresponds to the appearance of logical 1 at its direct output, which leads to the opening of transistor 5. In this case, the parallel loading of the controlled divider 6 frequency also ends and it is transferred to the counting mode. In the process of pulse subtraction (fig. 2a), at the output of the counting end, a rectangular pulse appears at the output of the controlled frequency divider 6 (fig. 2d), which, through the OR circuit 7, triggers 3. returns it via the R input to the initial zero state, which leads to the locking of the power transistor 5.

The duration of the rectangular pulses (Fig. 2c) formed at the output of the RS-flip-flop 3, and hence at the output of the transistor 5, will be equal to T - TcgM, where T3g is the period of the pulses of the driving oscillator T; M is the variable division factor of the controlled frequency divider 6 (the maximum value of M is chosen equal to Mmax. Tmax. / Tcg); T max the maximum allowable pulse duration of the power transistor 5,

When the division ratio of the controlled frequency divider 6 changes in accordance with the value of the control code 12 (the required pulse duration), the pulse duration (Fig. 2c) at the output of transistor 5 will change, which leads to pulse-width voltage regulation at the output of the converter.

For a converter operating on a power transformer, it is necessary to exclude the possible exceeding of the maximum permissible volt-second pulse area due to an increase in the voltage of the power source. For this purpose, voltage from the power source output (terminal 11) is fed through the matching unit 10 to the second input (Fig. 2e) of the comparator 9. The matching unit 10 provides for the cut-off of small values of the primary voltage, at which the maximum permissible value of volt-seconds - 5 times the pulse area at the output of the trap is not exceeded. nisistor 5. The first input of the comparator 9 receives the voltage (figd) from the output of the digital-to-analog converter 4, which decreases with the change in the state of the binary counter 2, at the moment of equal voltage (fig.2d, e) at the inputs of the comparator 9 the latter forms a pulse (Fig. 2g), which through the scheme OR 7 sets and then holds

5 R input trigger 3 in the zero state. As a result, a time interval is formed at the output of the RS-Trigger 3, the duration of which is proportional to the voltage at the second input of the comparator 9.

0 When the supply voltage is less than or equal to the cut-off voltage of the unit 10, the specified time interval is zero, with an increase in the supply voltage the time limit of the limitation also increases

5 pulse duration at the output of the transistor 5.

Thus, the introduction of a controlled frequency divider and new connections into the device allows to simplify it while ensuring the pulse-width control of the output voltage, to exclude the possibility of exceeding the permissible level of the volt-second area of the pulse and the saturation of the output transformer of the converter.

Claims (1)

Apparatus of the Invention A device for controlling a single-phase DC converter 0 comprising a master oscillator, the output of which is connected to the input for counting for decreasing a binary counter, the counting output for reducing which is connected to the S-input of the RS flip-flop, R-BXO5 the house of the OR element connected to the output, and the RS flip-flop output is intended to be connected to the control junction of the power transistor, and the group of information outputs of the said A binary counter 0 is connected to a group of inputs of a digital-to-analog converter, an output of a comparator connected to the first input, the second input of which is connected via a matching unit to a power supply terminal terminal 5, which, for simplicity, introduces a controlled frequency divider, an input for a reduction account, which is connected to the output of the master oscillator, the parallel load enable input is connected to the output of the RS flip-flop, and the output of the final account for a smaller input is connected to the output of the company to the first input OR, secondary comparator. IlllllllllllllllllllUllinillilllllini one I d, e f one FIG. 2