SU1697230A1 - Digital device for control over transistor inverter - Google Patents

Abstract

The invention relates to devices for pulsed voltage regulation and can be used as part of power supplies. The aim of the invention is to simplify the device and expand its functionality. The device contains a master oscillator 1, the first 2 and second 3 controlled frequency dividers and serially connected RS flip-flop 4, preamplifier 5 and transistor switch 6. The output of master oscillator 1 is connected to the counting inputs of controlled dividers 2 and 3 frequencies whose outputs are connected respectively, with the first and second inputs of the RS flip-flop 4, the output of the RS flip-flop 4 is connected to the setup input of the second controlled frequency divider. The presence of an additional pulse frequency channel allows two-zone control. 2 Il.

Description

cl

with

The invention relates to devices for pulsed voltage regulation and can be used in the composition of the secondary power supply sources.

The aim of the invention is to simplify the device and expand its functionality by providing both latitude and pulse frequency control.

FIG. 1 shows a functional diagram of the device; in fig. 2 - time diagrams that show his work.

A digital device for controlling a transistor inverter (Fig. 1) contains a master oscillator 1, the first 2 and a second 3 controllable frequency dividers and serially connected RS flip-flop 4, a preamplifier 5 and a transistor switch 6. The output of the master oscillator 1 is connected to the counting inputs

controlled dividers 2 and 3 frequencies, the outputs of which are connected respectively to the first and second inputs of RS flip-flop 4. In addition, the output of RS flip-flop 4 is connected to the setup input of the second controlled divider 3 frequencies. The controlled frequency divider 2 is designed as a serially connected divider 7 with a variable division factor and an uncontrolled divider 8.

The device works as follows.

The master oscillator 1 generates square-shaped pulses (Fig. 2a), the frequency of which

fs.r KMmax fnaKC.

where KMnax is the division ratio of the controlled divider 2 frequencies;

K is the division factor of the frequency divider 8;

ABOUT

about vj

N3 CO O

NMBKC is the maximum value of the variable division factor of the frequency divider 7;

fwaKc is the maximum operating frequency of the transistor inverter.

These pulses are fed to the counting inputs of the first 2 and second 3 controlled frequency dividers, the division factor is chosen according to the values of the digital frequency control codes 9 and the duration 10 of the pulse voltage at the output of the transistor inverter,

In the initial state, the RS-flip-flop 4 is in the zero state and, from its direct output, the logical O signal keeps the controlled divider 3 frequencies in the zero state from the setup R-input. In addition, this signal enters through the preamplifier 5, which serves to match the output of the RS flip-flop 4 to the input of the transistor switch 6, and, if necessary, for galvanic isolation, closes the transistor switch 6.

The pulses (Fig. 26) from the output of the controlled frequency divider 2, acting on the RS flip-flop 4, set it on the S-input to the one state, which corresponds to the appearance of the logical 1 at its direct output. When this occurs, the preamplifier 5 and the transistor switch b are opened, as well as the removal from the controlled divider 3 of the prohibition frequency for counting pulses (Fig. 2a) coming from the master oscillator 1. During operation, the controlled divider 3 frequencies at its output are is a rectangular pulse (Fig. 2d), which, acting on the RS flip-flop 4, returns it to the initial zero state via the R input, which causes the transistor switch 6 to be locked.

The duration of the rectangular pulses (Fig. 2c) generated at the direct output of the RS flip-flop 4, and hence at the output of the transistor switch 6

.gM

where T3.g is the period of the following pulses of the master oscillator 1;

M - variable division divider factor of 3 frequencies (maximum value of M)

Mmax T max / Teg,

t max - the maximum allowable pulse duration of the transistor inverter.

When changing the division factors of the first 2 and second 3 controlled frequency dividers in accordance with the values of the frequency control codes 9 and duration 10 (the desired frequency and pulse width of the output voltage) frequency-width-pulse control of the amplitude of the fundamental harmonic of the output voltage is performed transistor inverter. Thus, the introduction to the device

The first and second controlled frequency dividers allow in addition to the width-frequency control of the output voltage, which makes it possible to build more complex systems with digital correction of the voltage at the output of the transistor inverter due to the presence of an additional channel of the frequency-pulse control extend range

linear regulation due to lower output voltage by two-zone regulation: frequency to frequency corresponding to the lower limit of the output voltage at rated load, and further pulse-width, due to digital correction of the output pulse duration to adjust the frequency of the output voltage as up and down relative to a given.

Claims (1)

Invention Formula A digital device for controlling a transistor inverter containing a master oscillator, successively connected RS-flip-flop, preamplifier and transistor switch, characterized in that, in order to simplify and extend the functionality by providing both latitude and 5 and ° frequency-pulse control, the first and second controlled frequency dividers are entered into it, the outputs of which are connected respectively to the first and second inputs of the RS flip-flop, and their counting inputs are connected to the output of the master oscillator, and the output of the RS flip-flop is connected to the setup input of the second controlled frequency divider. FIG 2