SU1718364A1 - Four-phase step motor controller - Google Patents

Abstract

The invention relates to electrical engineering and can be used for multi-mode control of any four-phase reversing stepper motor. The purpose of the invention is the expansion of operational capabilities through the implementation of symmetric and asymmetrical switching modes. The device contains four power amplifiers 1.1-1.4 connected to the corresponding phases of the engine, a 2-clock bus, the first 3.1 and a second 3.2 D-flip-flops with combined clock inputs, three 4.1–4.3 unequalities, a reverse bus 5, a countable T-flip-flop 7 , the first 6.1 and the second 6.2 are the switching mode control buses, the first 8.1 and the second 8.2 are H-NOT elements, the four elements are AND 9.1-9.4 and the four elements are OR 10.1-10.4. 1 il. s yo

Description

The invention relates to the control of electrical machines in electrical engineering and can be used for multi-mode control of any four-phase reversible stepper motor.

A device is known for controlling a four-phase stepper motor, comprising a reversible pulse distributor, four AND elements, four OR elements, four power amplifiers connected to the corresponding phases of the motor, and a phase switching mode control bus.

The disadvantages of this device are the complexity of the circuit (taking into account the internal structure of its reversible pulse distributor) and the limited functionality due to the provision of only two modes of phase switching

The closest in technical essence to the proposed one is a device for controlling a four-phase stepper motor, containing four power amplifiers connected to the corresponding phases of the motor, a clock bus, first and second D-triggers with combined synchronization inputs, the first disambiguation element, the output of which is connected to D- information input of the first trigger, and the reverse bus connected to the first input of the first element of unequality. It also contains a second element of disambiguation, the inputs of which are connected to the reverse bus and with the direct output of the first trigger, and the output is with the D-information input of the second trigger.

The disadvantages of this device are the limited functionality and scope, due to the provision of only a pair mode of phase switching.

The purpose of the invention is the expansion of operational capabilities by implementing modes of symmetric alternating and asymmetric phase switching.

This goal is achieved in that a device for controlling a four-phase stepper motor, containing four power amplifiers, two D-flip-flops with combined synchronization inputs, a clock bus, two disambiguation elements, the first inputs of which are connected to the reverse bus, the outputs - with information inputs of the corresponding D- flip-flops, and the second input of the second discontinuity element is connected to the direct output of the first D-flip-flop, characterized in that, in order to expand operational capabilities by implementing symmetrical and asymmetric switching, a countable T-trigger, two AND-NOT elements, four AND elements, four OR-NOT elements, a third unequal element and two switching mode control buses connected to the first inputs of all AND-NOT elements are introduced, the output of the first of which is connected to the first inputs of all AND elements, * the second input is to the output of the second AND-NOT element, the second input of which is connected to the direct output of the countable T-trigger, the input of which is connected to the clock bus, the inverse output is to the second input of the third unequal element signatures, the first input of which is connected to the reverse bus, the output is to the synchronization inputs of D-flip-flops, the direct output of the first of which is connected to the second inputs of the first OR-NOT element and the second AND element, the inverse output is to the second inputs of the third OR-NOT element the fourth element AND, the direct output of the second D-trigger with the second inputs of the second element IL И Н Е and the third element И, the inverse output with the second inputs of the fourth element OR-NOT, the first element AND and the first element of disambiguity, the first inputs of the elements OR -NOT connect Nena with respective outputs of AND gates, and outputs - with the power amplifier inputs.

The drawing shows a functional diagram of a device for controlling a four-phase stepper motor.

The device contains four power amplifiers 1.1-1.4 connected to the corresponding phase windings W1-WIV of the motor, a clock bus 2 (T), the first

3.1 and second 3.2 D-flip-flops, the first 4.1, the second 4.2 and the third 4.3 elements of disambiguation, the reverse bus 5, the first 6.1 (Υι) and the second (Ug) switching mode control buses, counting T-trigger 7, the first 8.1 and second 8.2 elements AND-NOT, from the first to fourth elements AND 9.1-9.4 and from the first to fourth elements OR-NOT 10.1-10.4.

The device operates as follows.

To ensure one or another mode of phase switching of the stepper motor, the corresponding zero and one logic potentials are applied to the control buses of mode 6.1 and 6.2. Depending on the required order (direction) of phase switching, zero or one logical potential is applied to the reverse bus 5.

When applying clock pulses to the input 2 of the counting trigger 7, its push-pull switching occurs. The rectangular signals from its inverse output through the element 4.3 of ambiguity arrive at the synchronizing inputs of the D-flip-flops 3.1 and 3.2. As a result of this, through the clock cycle of pulses to bus 2, D-triggers 3.1 and 3.2 switch over. Moreover, if the order of switching the phases of the motor is specified (zero potential is applied to bus 5), then binary codes 00, 10, 01, 00 are periodically generated on the direct outputs of the D-flip-flops ..... and if the reverse order of phase switching is set (to bus 5 is logged with unity potential), then binary codes 00,01,11, 10,00, ... are periodically generated on the direct outputs of these triggers ... These codes pass through the corresponding logic elements 9.1-9.4, 10.1-10.4, and amplifiers 1.1- 1.4 power create a particular mode of switching the phases of the stepper motor. Moreover, if zero potential is applied to the bus 6.1 and any potential is applied to the bus 6.2, then an alternating phase switching mode is created for the Engine with codes at the outputs of the elements 10.1-10.4 0100, 0010,0001,1000, 0100, ... in direct order, and with codes 0100,1000,0001,0010,0100, ... in the reverse order. If a unit potential is applied to the bus 6.1, and to the bus

6.2 - zero potential, then a pair switching mode is created with codes at the outputs of elements 10.1-10.4: 1100, 0110, 0011, 1001, 1100, ... in the direct order and with codes 1100, 1001, 0011, 0110, ... at reverse order.

With the described two symmetric phase switching modes, the output signals of the counting trigger 7 do not actually reach the elements 9 and 10 (due to the blocking at the inputs of the elements 6.1 and 6.2 with the corresponding input control potentials).

The counting trigger 7 is introduced into the process of generating the output codes for switching the phases of the engine in the unbalanced mode, which is created when unit potentials are applied to both control buses 6.1 and 6.2. At the same time, the corresponding switching codes 1100, 0100, 0110, 0010, 0011, 0001, 1001, 1000, 1100, ... are formed at the outputs of elements 10.1-10.4, with direct order and codes 1100, 1000, 1001, 0001, 0011, 00Ю, 0110, 0100, 1100, ... with the reverse switching order.

The device is devoid of logical redundancy, i.e. it does not contain forbidden or inadmissible logical states, since all binary codes of D-flip-flops are used to form the corresponding phase switching modes. The initial state of the T-flip-flop also does not affect the normal operation of the device, since this only determines the temporal shift of the phase switching with respect to the input clock signals.

Claims (1)

Claim A device for controlling a four-phase stepper motor containing four power amplifiers, two D-flip-flops with combined synchronization inputs, a clock bus, two disambiguation elements, the first inputs of which are connected to the reverse bus, the outputs - with information inputs of the corresponding D-flip-flops, and the second input of the second the ambiguity element is connected to the direct output of the first D-trigger, characterized in that, in order to expand operational capabilities by implementing symmetric and asymmetric comm modes utation; a countable T-trigger, two AND-NOT elements, four AND elements, four OR-HE elements, a third disambiguation element and two switching mode control buses connected to the first inputs of all AND-NOT elements, the output of the first of which is connected to the first inputs, are introduced of all AND elements, the second input is to the output of the second AND-NOT element, the second input of which is connected to a direct output from an even T-trigger, the input of which is connected to the clock bus, the inverse output is to the second input of the third unequal element, the first input of which is connected to tire e reverse, output to the synchronization inputs of D-flip-flops, the direct output of the first of which is connected to the second inputs of the first OR-HE element and the second AND element, the inverse output - to the second inputs of the third OR-HE element and the fourth AND element, direct output of the second D-flip-flop - with the second inputs of the second element AND AND NOT and the third element AND, inverse output - with the second inputs of the fourth element OR-HE, the first element AND and the first element of disambiguation, the first inputs of the elements OR are NOT connected to the outputs of the corresponding elements AND , and exit - a power amplifier inputs.