SU1716615A1 - Coherent receiver of frequency-shift radio signals with continuous phase - Google Patents

Abstract

The invention relates to radio and can be used in systems for transmitting discrete information over radio channels with strict requirements for limiting bandwidth. The aim of the invention is to increase the reliability of reception and increase the limiting data transmission rate at a fixed radio signal sampling rate. To achieve the goal, an analog-to-digital quadrature converter and a clock generator with a sampling frequency close to the symbol frequency and simultaneous heterodyne input of the radio signal to the zero frequency region are introduced, when implementing a reference oscillation recovery system including a phase-locked frequency control unit and the input clock regeneration circuit and tracking the upper and lower frequencies of the transmission of discrete symbols of information, the spectral harmonics of which will be located in low frequencies The cost domain, as well as the optimal processing schemes were introduced with the decision on the transmitted symbol of information on the result of the accumulation of energy of the received signal on three symbols. 5 il. with C

Description

The invention relates to radio and, can be used in systems for the transmission of discrete information via radio channels with stringent requirements for limiting bandwidth.

A coherent receiver is known comprising a demodulator and a system for restoring reference oscillations with central f0 and symbolic fc frequencies. In this case, the phase-control auto-tuning system (PLL) of the reference frequency f0 includes two key devices controlled by pulses generated in the symbol synchronization system from the restored reference oscillation

symbol frequency f0. Thus, there is a cross-link between the two systems tracking the center fo and the symbolic fc frequency. ; A digital coherent receiver is known, in which the restored oscillation of the half-character frequency fc / 2 is used in the restoration of the reference oscillation at the center frequency fo, and there is also an interconnection between the two synchronization systems.

A disadvantage of the known schemes of coherent receivers is that synchronism in the channel of the central frequency f0 of the received signal is achieved only

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only after the synchronization of the symbol synchronization system, the stability of the operation of which directly depends on the frequency detuning in the channel tracking the central frequency fo. In the known coherent receiver circuits, there is a sequential two-dimensional search by the central frequency fo (carrier frequency) and the symbol frequency fc, which determines the presence of cross-links between the two synchronization systems when restoring the necessary reference oscillations. Sequential two-dimensional search at the specified frequencies significantly increases the time to synchronization compared to the one-dimensional search and creates a serious problem of entering the synchronization directly on the transmitted information radio signal, leading to the need to periodically incorporate a special synchro preamble into the transmitted radio signal for fast forced synchronization both synchronization systems. The effectiveness of entering into synchronism with respect to a special synchro-preamble is determined by its length (time interval) and the frequency of input into the information signal, i.e. the value of its time-specific content in the transmitted radio signal. Improving the efficiency of such synchronization reduces the speed of transmission of useful information,

The closest to the proposed technical entity is a coherent receiver, which contains two multipliers, two gated integrators, two crucial devices, a switch, a device for squaring the input radio signal and a system for restoring reference oscillations. In this case, the reference oscillation recovery system consists of two independent parallel PLL systems with doubled upper 2fe and lower 2fH symbol transmission frequencies, the spectral harmonics of which are formed as a result of squaring the input radio signal into a square, and the regeneration unit of necessary reference oscillations. Restored reference oscillations are:

fo 2fB - 2fH;

1 ± 2 soz (2l: f0t) -soz (2 fct / 4)

 ± cos (27rfBt) ± cos ();

0 5 0 5 0 5

0 5 0

five

Q ± 2sin (fot) -sin (2jr fct / 4) ± cos (2rcfBt) ± cos (27TfHt).

The presence of two characters in quadrature components 1 and Q, applied to the second inputs of the multipliers, is due to the sign uncertainty that occurs after dividing the 2fB and 2fH frequencies into two PLLs.

Building a system for restoring reference oscillations based on two independent PLL systems allows one to perform parallel one-dimensional search at frequencies 2fe and 2fH and to achieve extremely short time-matching for coherent receivers of frequency-manipulated radio signals with a continuous phase (in particular, MMC signals) directly transmitted informational radio signal. For this type of reference oscillation recovery system, there is no need to use synchro-preambula with the aim of shortening the time to synchronization.

Since the reference oscillations 1 and Q are restored with the sign uncertainty, the decision on the value of the information symbol at the receiver output has the same uncertainty. When information symbols are demodulated, a reverse operation effect takes place. In order to eliminate the sign ambiguity (to eliminate the effect of the reverse operation), it is necessary to additionally apply differential encoding and decoding of information symbols. This way of solving the problem of reverse operation leads to an additional functional and instrumental complication of the modem of the MMS signals.

The existing reference oscillation recovery system, in addition to the two PLL systems at twice the 2fe and 2fH frequencies, contains a squared radio input signal to form the corresponding spectral harmonics tracked by the PLL systems, as well as frequency dividers and mixers that are part of the regeneration unit of the necessary reference oscillations . These additional functional devices complicate the implementation of the reference oscillation recovery system, increase the instability of its operation, and reduce the overall hardware reliability.

Building a reference oscillation recovery system with squaring the input radio signal makes it very difficult to implement the entire coherent receiver completely in a digital inte gral form (for example, ADC and one universal gate array, CCL), as the speed of the input ADC and digital element base for the reference the oscillations will be determined according to the well-known Kotelnikov theorem, with a maximum frequency of 2fe: fA 4fB; fe fo + fc / 4, where td is the sampling frequency of the input radio signal, fc -. the frequency of transmission of information symbols. The digital integral implementation of the coherent receiver, in addition to reducing the weight and size parameters of the receiver design and much better manufacturability, makes it possible to achieve high stability of all functional units of the coherent receiver (especially the reference oscillation recovery system and multipliers) and to increase the reliability of the received information.

Taking into account that the structure of the narrow-band linear radio path preceding the ADC requires the fulfillment of the condition f0. 10D F, where D F is the spectrum width of the transmitted information signal (for signals from MMS D F 1.5 fc), the maximum possible information transfer rate will be much lower than the sampling rate of the input radio signal:

.

The aim of the invention is to increase the reliability of reception - and increase the limiting data transmission rate at a fixed radio frequency sampling rate.

FIG. 1 shows a coherent receiver structural diagram (letters of the Russian alphabet a, b, c, etc. denote some points in the block diagram of a coherent receiver); in fig. 2 - an embodiment of the implementation of the ACCP block on digital circuits; in fig. 3 — implementation of digital PLL systems; in fig. 4 and 5 are the timing diagrams of the signals explaining the operation of the coherent receiver (the corresponding timing diagrams are denoted by Russian letters).

The coherent receiver of frequency-controlled radio signals with a continuous phase (Fig. 1) contains an analog-to-digital quadrature converter (ADCC) 1, a clock generator (D) 2, the first and second multipliers 3 and A (P), the first and second blocks 5 and 6 phase locked loop (PLL), first and second gated drives 7 and 8 (СН), serially connected first register (REG) 9, first and second combinational

adders 10 and 11 (CM), adder 12 modulo two (M2) and the first D-flip-flop 13 (TR), serially connected second register 14, direct-to-additional converter 15 to additional (PR), multiplexer 16

0 (MPL), the third combination adder 17 and the third register 18, the fourth combinational adder 19, the accumulative adder 20 (NS), the first element OR 21 and the first and

5, the second delay blocks 22 and 23 (BLS), as well as the second and third D-flip-flops 24, 25 and the second element OR 26. The first input of the ACC 1 is the input of the coherent receiver, and its first and second outputs are connected to the corresponding the inputs of multipliers 3 and 4, the third and fourth inputs of which are connected to the first and second outputs of the first and second blocks 5 and 6 of the CEFAC, respectively, the first and second inputs of which are connected to the first and second outputs of the corresponding multipliers 3 and 4, the third outputs of blocks 5 and 6 CFACs are connected to the first and second input Raman adder 19 mi.

0. The second and third outputs of the cumulative adder 20 are connected respectively to the second and first inputs of the elements OR 21 and 26, and the output of the element OR 26 is connected to the third inputs of blocks 5 and 6

5 TsFAPCH. The second outputs of multipliers 3 and 4 are connected to the first inputs of gated drives 7 and 8, the outputs of which are connected to the first inputs of registers 9 and 14, respectively. The second inputs of tunable drives 7 and 8 and registers 9 and 14 are connected to the output of delay block 22, the output of the register 14 is connected to the second input of the multiplexer 16, the second output of which is connected to the second output

5 combinational adder 10. The output of register 18 is connected to the second input of combinational adder 11, the output of which is connected to the first input of D-flip-flop 24, the output of which is connected to the second

0 input of the modulo two adder 13. The output of the clock generator 2 is connected to the second input of the ASCC, with the third inputs of the gated drives 7 and 8, the fourth inputs of the TsFAPC blocks and the second input

5 cumulative adder 20, the first output of which is connected to the first input of the D-flip-flop 25, the output of which is connected to the third input of the multiplexer 16. The second inputs of the register 18, the element OR.26, D- triggers 24 and 25 are connected to the output of the element OR 21, the output the register 9 is connected to the inlet of the combinational adder 17, and the output of the delay unit 23 is connected to the second input of the D-flip-flop 13, the output of which is the output of the coherent receiver.

Block 1 (Fig. 2) contains an analog-to-digital converter 27 (ADC), D-flip-flops 28 and 29 (TR) and a distributor 30.

Blocks 5 and 6 (Fig. 3) contain cumulative adders 31 and 32 (NS), register 33 (REG), D-flip-flop), a direct code to additional (PR) converter, digital filter 36 (DF), and a digital synthesizer 37 counts (CSO).

Coherent receiver works as follows.

In block 1 ADC, the input radio signal with the center frequency f0 by appropriately selecting the sampling frequency RD heterodynamically low-frequency region and is converted into digital samples of two quadrature components represented in the form of a binary direct code for positive and additional code for negative samples. A possible embodiment of the ACC block is shown in FIG. 2. In the A / D converter 27, digital samples of the input radio signal are formed with a sampling frequency td selected from the ratio

fA 4f0 / (4k ± 1),

where k is the number of the harmonic fA closest to f0. At the same time, multiplying the digital samples of the input radio signal by the samples of the sinusoidal and cosine oscillations is reduced to allocating the even components in the channel of the cosine component and odd numbers in the channel of the sinusine signal and inverting the sign of each second reference in both channels. All these functions are performed by the distributor 30 according to the control signals Q1, Q1, Q2, and Td) formed from a pulse sequence of clock pulses with a frequency ffl of two D-triggers 28 and 29. With this construction of block 1 ADC, the sampling frequency can be The dock is smaller than the center frequency of the input signal spectrum, and is closer in magnitude to the symbol frequency fc. As a result, independent parallel PLL systems (blocks 5 and 6) will track, up to phase, the upper and lower frequencies of transmission of discrete information symbols, the spectral harmonics of which will be located within the frequency interval (-fc; + fc). So essentially

the clock frequency of the entire digital receiver is reduced, equal to the frequency of the disk-. retesting the input radio signal, and accordingly the speed limit increases

transmission of information.

From the outputs of the distributor 30, which are the outputs of block 1 ADCS, digital samples of quadrature components arrive at the first and second inputs of both the multipliers 3 and 4 (Fig. 1), performing complex multiplication of the input signal samples with samples of the reference oscillations tracked by blocks 5 and 6 PLL. To simplify the structure of complex multipliers, the reference oscillations (subject to multi-level quantization of the input radio signal) can be binary. From the first and second outputs of blocks 5 and 6 samples of binary reference oscillations

0 arrive at the third and fourth inputs of multipliers 3 and 4, from the outputs of which the imaginary and valid components of the multiplication results (Fig. 4a, b, c, d) go to the first and second inputs of the corresponding blocks 5 and 6. A possible embodiment of the blocks 5 and 6 is shown in FIG. 3 is a digital implementation of a costas circuit with a cosine (real) limiter. At the exit

0, a code converter 35 generates a digital PLL discriminator code that enters a digital filter block 36, the output of which generates a control code supplied to a digital sampling signal generator block 37, where the binary samples of the reference oscillations are synthesized with the required frequency and phase. The outputs of the DSP block 37 are the first and second outputs of the PLL blocks 5 and 6. AT

In the steady state tracking mode of blocks 5 and 6, the discriminator's digital code is close to zero, and the control code at the output of digital filter 36 is equal to a certain constant value.

5 The control codes from the third outputs of blocks 5 and 6 are fed to the inputs of the combinational adder 19, which is included in the sync pulse regeneration circuit, consisting of the combinational adder 19, the accumulative adder 20 and two elements OR 21 and 26. The total control code arriving from the output of the combinational adder 19, cyclically accumulates in the cumulative adder 20 until moments

5 its overflow. The first, second and third outputs of the cumulative adder 20 are the outputs of its overflow bit and the two most significant bits. Level 1 appears at the output of the overflow discharge with a frequency equal to the difference between the upper TV and the lower fH of the manipulation frequency of the input frequency-switched signal with a continuous phase, and regardless of its Doppler shift and in strict accordance with its phase: fr fa - fa. For frequency manipulation with a minimum shift (MMC), fi fc / 2 (Fig. 4a), where ft- is the frequency of the information symbols. At the output of the logical element OR 21, the sync pulses, also corresponding to the appearance of level 1, have the following frequency — fc (Fig. 4), and at the output of the OR element 26 - the frequency fs 4fi 2fc (Fig. 4k). The sync pulses thus regenerated are fed to the control inputs of the corresponding blocks of the Coherent Receiver circuit (Fig. 1). The delay blocks 22 and 23 serve to match the arrival times of the clock pulses with the propagation time of the digital samples of the processed signal.

In gated accumulators u8, the actual components of the results of multiplying the input signal and the reference oscillations (Fig. 46, d), coming from the second outputs of multipliers 3 and 4, accumulate over a time equal to the duration of the transmitted information symbols, otherwise, the follow-up period of the control reset pulses ( Fig. 4i). Buffer registers 9 and 14 serve to store the accumulated samples of signals. In the time interval between the reset pulses that zero the gated drives 7 and 8.:

The combinational adders 10, 11 and 17, multiplexer 16, register 18, adder 12 modulo two and D-flip-flop 24 implement an optimal three-character algorithm for processing the received signal, which provides the minimum demodulation error of the information symbol. In this case, the register 18 and the D-flip-flop 24 perform the function of blocks of delay for the duration of one character, the function of the threshold device is performed by the combinational adder 11, the output of which is the output of its sign (senior) bit, and the Modulator Two adder serves as a multiplier of digital binary signals. Evaluation of the current transmitted information symbol is formed already at the output of adder 12, but its precise temporal reference to the sequence of clock pulses of the symbol frequency fc is performed in a D-flip-flop 13, the output of which is the output of the coherent receiver. The operation of the blocks described is illustrated in FIG. 4 and 5: time diagrams d, e, f, m-t.

From the output of the clock generator 2, the clock pulses with a following frequency equal to the sampling frequency td are sent to the second input of the 1 ACC block, to the third inputs

gated drives 7 and 8, to the fourth inputs of blocks 5 and 6 of the PLL and to the second input of the cumulative adder 20, which is necessary to ensure their functioning.

The process of demodulating information symbols is illustrated by the time diagrams shown in FIGS. 4 and 5, which shows the complete exclusion (as opposed to the prototype) of the effect of feedback. The phase jumps of the reference oscillations on p occur during the operation of a coherent receiver under the influence of noise (disturbance) spikes, the appearance of which has a small, but, nevertheless, finite probability.

The phase uncertainty of the restoration of the reference oscillations leads to the same uncertainty of the sign of any of the real components (Fig. 46, c) of the results of the complex multiplication

input signal to the reference oscillations. In the timing diagrams of FIG. 4 and 5 the dashed lines show the process of demodulation during the jump phase of the reference oscillation (for example, in block 5 of the PLL,

FIG. one). In addition to the inversion of the corresponding valid component (Fig. 46, e), in accordance with the changed control code that enters the third output of the PLL unit 5 at the first input of the combination adder 19, the phase of the sync pulse sequence with the half-symbol frequency (Fig. 4a) will also change, will lead to inversion (phase shift) of the sync signal (Fig. 4k); work manager

code converter 15 and multiplexer 16. The further demodulation process is shown by dotted lines in the following diagrams of figures 4 and 5. As a result, the sequence of demodulated information symbols will be the same as in the absence of a phase jump of the reference oscillation. Thus, unlike the prototype, the implemented optimal (Three-character) algorithm

demodulation is invariant to the phase uncertainty of the recovered reference oscillations, i.e. it completely eliminates the inverse effect of demodulating information symbols. Thereby

The reliability of receiving discrete information is significantly improved.

Claims (1)

Coherent receiver of frequency-modulated radio signals with continuous phase, the contents of the first and second multipliers, the first and second blocks of phase-locked loop, and the first and second gated drives, which are used to increase the reliability of reception and increase the maximum information transfer rate fixed frequency sampling of radio signals, introduced analog-to-digital quadrature converter, clock generator, serially connected first register, first and second combinational adders, modulo two and first D-flip-flop, sequential Boundedly connected second register, direct code to additional converter, multiplexer, second combination adder and third register, serially connected fourth combination adder, accumulative adder, first OR element and first and second delay blocks, and second and third D-triggers and the second OR element, with the first input of the analog-to-digital quadrature converter being the input of a coherent receiver, and its first and second outputs are connected to the corresponding inputs of the first and second surrender ,. the third and fourth inputs of which are connected to the first and second outputs of the first and second phase-locked loop units, respectively, the first and second inputs of which are connected to the first and second outputs of the respective multipliers, the third outputs of the first and second blocks of the phase locked loop are connected to the first and second inputs of the fourth combinational adder, the second and third outputs of the cumulative adder - respectively with the second input of the first and the first input of the second element OR, and the output of the second element OR - with the third inputs of the first and second blocks of the phase-locked loop, the second outputs the first and second interchangers - with the first inputs of the first and second gated drives, respectively, the outputs of which are connected respectively to the first inputs of the first and second registers OOB, the second inputs of the first and second gated drives, the first and second registers are connected to the output of the first delay block, the output of the second register - the second input of the multiplexer, the second output of which is connected to the second inputs of the first Raman adder, the output of the third register to the second inputs of the second Raman ummatora whose output is connected to a first input the second D-flip-flop, the output of which is connected to the second input of the modulo two adder, and the second inputs of the third register of the second D-flip-flop and the second element OR are connected to the output of the first element OR, clock generator output - with the second input of the analog-to-digital quadrature converter, with the third inputs of gated drives, the fourth inputs of the phase locked loops frequency and the second input of the cumulative adder, the first output of which is connected to d by the first input of the third D-flip-flop, the second input and output of which are connected respectively to the output of the first OR element and the third input of the multiplexer, the output of the first register to the second input of the third combinational adder, the output of the second the delay unit is with the second input of the first D-flip-flop, the output of which is the output of the coherent receiver. FIG. I. SP Ch ate N N (rt o Yu with about about SP Distributor V N o Accept information symbols k {{o o 4 ooo {I o 1 -. about Interpretation of sample codes: a - f, k - p. Igill J til 41 FF miminnit. ;. Tlillii.; tit .j .....; 1; .TIPP ..; ii-ii iiiii 4l; iii: i; .four ; : Ts111N1111 iiiii × B ttmpmpptit timii f tshchlug r. ih .... F 4t Mii to J TEI IirnL rTlCJr r I i i i i i i i i i i i i i i i i i i i i i i m i i i i ter. :,.four. 55 F th step th. 41 i i i i i i Accepted Simulation  {{О О {О О, О t (jQ i, О