SU1711236A1 - Back-up byte-wide memory - Google Patents

Abstract

The invention relates to computing technology / namely to redundant storage devices, and can be used in the construction of storage devices of highly reliable computers. The aim of the invention is to expand the field of application of the device by providing a Record of information both in the form of a word and half-word. The device contains two correction blocks, two working memory blocks and two additional memory blocks, the discharge grids of which are divided into two parts. Each memory unit is equipped with two control units, which include a key, a switch and a register. The device allows you to record both words and half words with overwriting information and the simultaneous elimination of random failures. 1 il. J

Description

The invention relates to computing, namely, to redundant storage devices, and can be used in the construction of storage devices of highly reliable computing systems.

The purpose of the invention is to expand the field of application of the device by providing the recording of information in the form of a word / and a half-word.

To explain the essence of the invention, one half-word of information received in a memory is called the first byte, and the other half-word is called the second byte. Each byte of incoming information is encoded in accordance with the rule of a non-binary two-redundant correction code to form a half-word. In this case, the first half of the bits of all memory blocks correspond to the half-word code of the first byte, and their second parts correspond to the half-word code of the second byte.

second parts. When writing information in the form of a word (i.e., both bytes), code-half-words-first and second bytes are sent to the device inputs, which are written to the corresponding parts of the bits of the memory blocks (working and additional). Writing only one byte firstly, in all memory blocks, the half-word of another byte is pre-read from them, which is entered into the corresponding registers, and then carried out by: writing to the memory blocks readable to the device of the code half-word and the previously read half-word. Note that the previously read half word when one of the memory blocks fails may be non-code.

Thus, when writing a byte, the corresponding half-word is written into one part of the bits of all memory blocks, and information is overwritten.

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in other parts of the bits of these blocks. If one of the memory blocks (working or additional) fails, an error may occur in both parts of its bits. Then the error in the first part of the bits of this block is corrected in the correction block (corrector) of the first byte when reading reliable information from the first parts of the bits of three healthy memory blocks, and the error in the second part of the bits of the bad memory block is corrected in the second byte . Thus, the device maintains fault tolerance, i.e. its operability, in the event of a malfunction. One of the memory blocks when recording information in the form of both a word and a half-word.

Increased reliability is associated with eliminating the consequences of accidental failure in one of the memory blocks due to the fact that during byte overwriting the pre-read information for writing to the registers is removed from the outputs of the corresponding corrector, thereby eliminating the random error.

The drawing shows the functional scheme of the proposed device.

In the drawing, the following notation is accepted: 1 — the inputs of the code half-word of the first byte, 2 — the inputs of the code half-word of the second byte, 3-10 — keys, 11-18 — registers; 19-26 are switches, 27 and 28 are working memory blocks, 29 and 30 are additional memory blocks, 31 is the first byte correction block, 32 is the second byte correction block,

33- control inputs of switches 19-22,

34- switch control input 23-26,35 - control key input 3-10, 36 and 37 - control inputs of registers 11-18, 38 - outputs of the first .byte, 39 - outputs of the second byte.

The device consists of working memory blocks 27 and 28, additional memory blocks 29 and 30, correction blocks 31 and 32, and eight control blocks (shown in the drawing e by a dotted line). Each control unit (for example, the first ones on the left in the drawing) contains a register ( 11), key (3) and switch

nineteen).

The size of each memory block is the same and is equal to b (b is even), so that the input size of the output of the output of each part of its bit grid is b / 2. The number of input bits of each register 11–18 is L / 2 and equals the number of input bits of each key 3–10. The same value is equal to the number of bits of their outputs. The number of bits of the inputs of each switch 19-26 is equal to b (b / 2 at each input), and the number of bits of output is b / 2. In addition, each switch and key have one control

input, and each register - two. The bit length of the input code half-word of the first byte is equal to the bit width of the input code half-word of the second byte and is 2b. The bit size of the input of each correction unit is 2b and is equal to the bit size of its outputs (each output contains b / 2 bits).

The device operates according to the following algorithm.

The 10 b-bits of the grid (the number of bits) of each written byte is divided into two equal parts, and each such part is considered as an element of the power field 2 (b / 2). Each byte of the received binary information is thus equivalent to two characters from. the floor These two characters are in accordance with the coding rule of a non-binary, two-redundant correction code correcting

20 errors in one character, two more characters are added, as a result of which the code half-word of this byte is formed. The length of each of these code halfwords is equal to four characters of the field GF 2 (b / 2) or 2b

25 binary digits dam. The code half word of the first byte goes to the inputs 1 of the device, and the code half word of the second byte goes to the inputs 2.

When both bytes are written at once, a low potential is applied to the equalizing input 35 of keys 3-10, with the result that these keys are closed and the data from inputs 1 and 2 are fed to the inputs of the memory blocks. In this case, the control input 37 registers

35 11-18 a high potential is applied, as a result of which these registers are in the high output resistance mode, and the value of the signals at the control inputs 33 and 34 of the switches 19-26 does not matter.

0 b-bit grids of the memory units are also split in half /, with the code half-word of the first byte written in one part, and the code half-word of the second byte written in other part.

5 For example, in the first part of the additional memory block 29, the third character of the code half-word of the first byte is written, and in the second part, the third character of the code half-word of the second byte.

0 When writing only one byte, the procedure is divided into two stages - preliminary reading from memory blocks and subsequent writing to them. In this case, the control input 35 of the keys 3-10 receives a high potential, as a result of which they open and do not affect the further process, and the control input 37 of the registers 11-18 has a low potential, which prevents them from going into high output impedance.

The second inputs of the switches 19-22 receive information from the outputs 38 of the equalizer 31, and the second inputs of the switches 23-26 from the outputs 39 of the corrector 32. In accordance with the structure of the correcting code used, the grid of the outputs of each correction block is divided into four equal the parts corresponding to the four symbols of the floor GF 2 (b / 2), and each such part forms one of the four outputs of this correction block. The splitting is performed in accordance with the rule of formation of code half words of the first and second bytes.

Information is sent to switch 19 from the first output of corrector 31, to switch 20 from the second output, to switch 21 from the third output, to switch 22 from the fourth output. Similarly, the switch 23 receives information from the first output of the equalizer 32, to the switch 24 from the second output, to the switch 25 from the third output, to the switch 26 from the fourth output.

If a random failure occurs in one of the memory blocks, after preliminary reading, the correct information is sent to the switches 19-22 or 23-26, which leads to the elimination of the consequences of such a failure.

Consider the case of recording the first byte. During pre-read, registers 11–18 operate in write mode, which is achieved by applying a low potential to their control input 36. In this case, a low potential is supplied to the control input 33 of switches 19-22, as a result of which they pass information from the inputs 1 of the device to registers 11-14, and a high potential is supplied to the control input 34 of switches 23-26, and they pass to registers 15-18 information from the outputs of block 32 correction of the second byte.

Thus, when pre-reading, the half-word of the first byte is written to the registers 11-14, and the information read from the second parts of the bits of the memory blocks 27-30 and passed through the correction block 32 is written to the registers 15-18. If an accidental failure occurs in one of the memory blocks, it is corrected with this procedure, which leads to an additional increase in reliability. After the preliminary reading, information is written to the blocks 27-30 of information from the regression module 11-18, which is carried out by supplying the high potential registers 11-18 to the control input 36. In this case, information from registers 11-14 is recorded in the first parts of the bits of blocks 27-30 of memory, and information from registers 15-18 in the second parts of the bits of these blocks. As a result, the first half of the first byte is written into the first parts of the bits of the memory blocks and the information is overwritten with a correction to the possible failure of the second parts of the bits of these blocks.

Similarly, the second byte is written. The only difference is that in the case of preliminary reading, a high potential is applied to the control input 33 of the switches 19-22, and a low potential to the control input 34. The switches 23-26. In the bits of the second parts of the memory blocks, the code half-word of the second byte is recorded, and the information is overwritten with the correction of possible failure from the bits of the first parts.

Both when writing a word and writing a half-word, when all the memory blocks work correctly, two code half-words are stored in their cells of the same name. Failure of one of the memory blocks can lead to an error in only one character in each of these code half words.

When reading, the information from the bits of the first parts of all the memory blocks goes to the corresponding bits of the input of the first byte correction unit 31, and from the bits of the second parts to the corresponding bits of the input of the second byte correction block 32. If one of the memory blocks malfunctions or when they function correctly, the first half byte code 31 outputs get the first byte codeword, and the second byte code half word is output at outputs 39 of the second byte correction block 32. Therefore, when one of the memory blocks fails, the memory does not malfunction, i.e. initial fault tolerance is maintained.

This algorithm of operation of the memory device is provided by feeding to the control inputs 33-37 of the above-described sequence of switching signals of the operating modes of the keys, switches and registers. These signals can be generated, for example, in a computer based on a program written according to this algorithm. A computer can also encode the first and second bytes.

Thus, the invention, as compared with the prototype, allows the device to expand its field of operation by ensuring that information is recorded both as a word and a half-word while maintaining its fault tolerance and to achieve additional reliability improvements by eliminating the consequences of successive failures.

Shadow-Ratio Formula A backup byte-memory device containing two working and two additional memory blocks, two correction blocks, the outputs of which are informational outputs of the device, characterized in that, in order to expand the application area by providing a record information, both in the form of a word and a half-word, control blocks are entered into it by the number of half words, each of the control blocks contains a register, a switch and a key, whose information input is one of the

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formation inputs of the device and connected to the first information input of the switch, the output of which is connected to the information input of the register, the output of which is connected to the output of the key and connected to the corresponding information input of the corresponding block gamma, the output of which is connected to the input of the corresponding correction block, the corresponding output of which is connected to The second information input of the switch, the control inputs of the register, the switch and the key are the control inputs of the device.

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Claims (1)

Claim A redundant storage device with a byte recording, containing two working and two additional memory blocks, two correction blocks, the outputs of which are information outputs of the device, characterized in that, in order to expand the scope by providing information recording in the form of a word or a word , control units are introduced into it according to the number of half-words, and each of the control units contains a register, a switch and a key, the information input of which is one of the information inputs of the device and it is single with the first information input of the switch, the output of which is connected to the information input of the register, the output of which is connected to the output of the key and connected to the corresponding information input of the corresponding Memory block, the output of which is connected to the input of the corresponding correction unit, the corresponding output of which is connected to the second information input of the switch , the control inputs of the register, switch and key are the control inputs of the device. fifteen '