SU1711148A1 - Modulo k adder - Google Patents

Abstract

The invention relates to computing and can be used in the construction of systems for the transmission and processing of discrete information. The aim of the invention is to reduce the amount of equipment. The adder modulo k () contains units of unitary summation, a unit of summation of unitary codes, including blocks of addition, a binary coder. Each node contains an element OR NOT. modulo two, element I with parallel-connected inputs, which are the inputs of the summation parts of the adder, and the KOTORYH outputs are connected to the block inputs with indices, (2M) mod k, (21) mod k, respectively (, 2.3.4). When the addends X and Y are applied to the inputs of the adder, single signals appear at the outputs of nodes with indices l ((Xj + Yi) 2nd) mod k. The codes from the outputs of the nodes are summed by the add blocks, while the outputs of the add block of the p-ro column will be a single signal with indices I (X + Y) mod k, which is fed to the inputs of the encoder with indices equal to the numbers of the single bits in the binary representation of the number ( X + Y) mod k. In this case, the outputs of the encoder will be a binary code number (X + Y) modk. 1 il. U) C

Description

The invention is computerized and can be used to build systems for the transmission and processing of discrete information.

The aim of the invention is to reduce the amount of equipment.

The drawing shows a modulo-adder circuit.

The modulo-13 adder contains four nodes 1.1-1.4 unitary sum, unit 2 summation of unitary codes, including blocks 3.1, 3.2, 3.3 addition, binary encoder 4.

Node 1.1 (, 2,3,4) unitary summation contains the element OR NOT 5, the adder 6 modulo two, the element 7 with parallel-connected inputs.

Block 3.1 is made in the form of 12 groups 8.1-8.12 of elements AND, the outputs of elements AND of each group 8.I are connected to the inputs of the element OR 9.1, the output of which is the output of a block with an index.

Each AND element of group 8.1 is connected by inputs to the outputs of blocks 3.2 and 3.3, forming at the inputs one of the combinations of indices of their outputs, the sum of which modulo k is I. At the inputs of elements And of group 8.1, non-repeating combinations of indexes of the outputs of the Ii-Hz blocks are formed 3.1

WITH

 + 12NO + 3.3 + 0.4 + 12.5 + 11} for + 12X1 +3.4 + 0.6 + 11.0 + + 4.5 + 12}

for I5 {h + + 3.5 + 0, 6 + 12. 1 + 4} for {li + + 4, 3 + 3, 6 + 0} for {And + + 7, 3 + 4. 4 + 3} for {И + 12ИО + 8, 1 + 7.4 + 4, 5 + 3} for {li + + 8, 2 + 7. 5 + 4. 6 + 3} for (And + + 7, 2 + 8, 6 + 4} for {And + + 7, 0 + 11, 3 + 8} for {h + I2H5 +7.1 + 11.0 + 12.4 + 8}

In block 3.2, the additions at the inputs of an element VI of group 10.) are implemented the following binations I + g of the output indices of the nodes and 1.2 unitary summation:

The outputs of the AND elements of groups 10.3 and 10.5 are connected to the inputs of the elements OR 11.3 and 11.5, respectively, the outputs of which are the outputs of the add block 3.2 with the subscripts 1 2 and I 4.

In block 3.3 of the addition, the following combinations li + Iz of the output indices of nodes 1.3 and 1.4 of unitary summation are implemented at the inputs of the elements And of each group 12.1:

0 {H + i2HO + 0} 3 {li + hHO + 3, 8 + 8} 4 {I | + I2} {4 + 0} 7 {H + + 3}

8 {li + l2HO + 8.8 + 0} 11 {ti + + 3} 12 {h + 2H4 + 8}

The outputs of the AND elements of groups 12.2 and 12.5 are connected to the inputs of the elements OR 13.2 and 13.5, respectively, the outputs of which are the outputs of block 3.3 with indices and.

Adding blocks can be of another design, including multi-threshold elements connected by inputs to the outputs of the addition blocks of previous columns or units of unitary summation with the same indices, and outputs from the inputs of elements And groups. At the same time, at the inputs of each element and group, all combinations of indices of the same type are realized, obtained by permuting the elements, that

additionally reduces the amount of equipment.

The operation of the adder is as follows.

When submitting the codes of the X and Y terms to

adder inputs single signals appear at the outputs of nodes 1.1 of unitary summation with indices (Xi + Yi) 2M) mod k.

Codes from the outputs of nodes 1.1 of unitary summation are summed by blocks 3.J

addition of block 2 summation of unitary codes, while the outputs of the block of addition of the p-th column with the index (X + Y) mod k will be a single signal that is fed to the inputs of the elements 4.f of the binary encoder 4

with numbers K equal to the numbers of unit bits in the binary representation of the number (X + Y) mod k. At the outputs of the encoder 4 will be the binary code of the number (X + Y) mod k.

Thus, the proposed modulo-k adder provides a reduction in the amount of equipment.

Formula of invention Modulo adder containing

log2 (k + 1) units of unitary sum, unit of summation of unitary codes modulo k and a binary encoder, the outputs of which are connected to the outputs of the modulo adder, k. and inputs are connected to

the outputs of the unit of summation of unitary codes modulo k, the groups of inputs of which are connected to the outputs of the corresponding nodes of the unitary summation, the inputs of which are connected to the inputs of the corresponding bits of the first and second operands of the adder modulo k, each node of the unitary summation contains the element OR NONE. element modulo two and the element And, the first and

the second inputs of which are connected to the corresponding inputs of this unitary summation node, and the outputs are connected to the outputs of this unitary summation node, and these outputs have indices li ((H) w) mod k, where .2.3; W is the weight of the bits of the operands, the inputs of which are connected to the inputs of this unitary summation node, so that, in order to reduce the number of equipment. the unitary code summation block contains addition blocks forming columns, the inputs of the addition blocks of the first column are connected to the outputs Pf of the groups of inputs of the summation block of unitary codes (Ki 2), and the inputs of the addition blocks of subsequent columns are connected to the outputs EI of the addition blocks of the previous columns (fi 2, ie {1jlog 2 (k + 1) -1}),

the outputs of the last column addition block are the outputs of the unitary code sum block.

Claims (1)

Claim A modulo k adder containing] log ₂ (k + 1) [unitary summation nodes, a unitary code summation unit modulo k, and a binary encoder whose outputs are connected to the adder modulo outputs, k. And the inputs are connected to the outputs of the unitary code summation unit modulo k, the group of inputs of which are connected to the outputs of the corresponding units of unitary summation, the inputs of which are connected to the inputs of the corresponding bits of the first and second operands of the adder modulo k, with each unit of the unitary summation contains the element And LI-HE, the addition element modulo two and the element I. The first and second inputs of which are connected to the corresponding inputs of this unitary summation node, and the outputs are connected to the outputs of this unitary summation node, and these outputs have indices ii = ((E = l) w) to, where 1 = 1.2.3: ω is the weight of the bits of the operands, the inputs of which are connected to the inputs of this unitary unit summing unit, characterized in that, in order to reduce the amount of equipment, the unitary unit summing unit contains addition units forming columns, and the inputs of the blocks with the positions of the first column are connected to the outputs ft of the groups of inputs of the unit of summing unitary codes (th> 2), and the inputs of the addition blocks of the subsequent columns are connected to the outputs b of the addition blocks of the previous columns (Γ,> 2, ifc '{1j! og2 (k + lX -1}), the outputs of the addition block of the last column are the outputs of the unit of summation of unitary codes.