SU1709505A1 - Binary sequence generator - Google Patents

Abstract

The invention relates to a pulse [technique and can be used in instrumentation engineering. The purpose of the invention, the expansion of functional capabilities due to the possibility of changing the structure of the formed sequences, is achieved by introducing into the binary sequence generator a group of elements AND 7.1-7.p. delay elements 10-12, a group of 13.1-13.3.k blocks of comparison, a memory block 14, an OR-NOT 16 element, a pulse counter 20, a single pulse former 22, an adapter 23, start bus 24 and the formation of new functional connections . The drawing also shows: modulo two adder 1, shift register 2, trigger signal, AND 4, 18, and 19 elements, 5 clock pulse generator, rec ^ gistr 6. pulse counter 8, delay element 9, comparison unit 15, OR element 17 , element NOT 21. 2 Il.

Description

The invention relates to a pulse technique and can be used to generate binary sequences of operatively tunable in composition and order of formation of the constituent code sets depending on the needs of monitoring (diagnostics) digital objects.

A pseudo-random number generator is known comprising a series-connected synchroactor, a shift register and a linear feedback block.

A disadvantage of the known device is the impossibility of using it to carry out a targeted synthesis of complex composite binary sequences, which ensure simultaneously the completeness of testing of digital objects and the selection and elimination of forbidden codes, the analysis of generated binary sequences.

The closest in technical essence and effect achieved is a device containing a serially connected modulo-two adder and a shift register, connected in series by a trigger and an element, the output of which is connected to the shift control input of the shift register, as well as a generator of sync tacts.

The disadvantage of this technical solution is the invariable sequence of binary codes for all scanned objects, which makes it impossible to excite certain sequential (containing memory elements)

digital objects. In addition, the known technical solution does not allow the targeted synthesis of test

influences and analyzing the flow of generated binary codes (determine the number of different binary generation codes or the length of the generation packet, determine if the package of generated codes contains any particular code and at what cycle it is generated, determine the order of the codes following) test synthesis and evaluation of the effectiveness of testing certain digital objects in non-standard situations.

These drawbacks of the known technical solutions result in low efficiency of monitoring and diagnostics of digital objects using pseudo-random codes.

The aim of the invention is to enhance the functionality of the generator by changing the structure of the generated sequences.

The goal is achieved by the fact that in a binary generator, a sequence containing a serially connected modulo two and an n-bit shift register) are connected in series with a trigger and element I. whose output is connected to the shift control input of the shift register, as well as a sync generator, the modulo two adder's input is connected to the bus of a simple logical unit, the issue register, the group of elements I, the address counter, the first, second, third and fourth delay elements, the element group are entered comparing, ROM, comparing element, the first and second OR elements, second and third AND gates, packet counter, NOT element, a single pulse generator and the adapter.

Due to the input of the indicated elements in the feedback register chains of the shift register, the binary sequence generator is operatively reorganized so that binary sequences are formed at the generator output, differing from each other in composition and / or sequence of the Binary codes, which provides control from the composition the binary sequence of forbidden codes while maintaining the G1 completeness of testing the control object, the generation of composite binary sequences to increase the field notes of testing for a variety of, x different coding polynomials (inverse polynomials (Connections) with automatic reorganization of the generator in a single generation procedure.

Fig, 1 shows the block diagram of the device; FIG. 2 is a block diagram of an adapter.

The binary sequence generator contains modulo 2 and n-bit connected in series

shift register 2, connected in series trigger 3 and element 4, the output of which is connected to the shift control input of shift register 2, and a generator

synchrotacts 5. The input of the adder 1 modulo two is connected to the bus constant logic unit. The output register 5, the group of elements 7, the address counter 8, the first 9, the second 10, the third IT and the fourth 12 delay elements, the group of comparison elements 13, the ROM 14, the comparison element 15, the first 16 and the second

17 elements OR, second 18 and third 19 elements AND, packet counter 20, element NOT

21, a single pulse shaper 22 and an adapter 23. A group of outputs (1 ... n) of shift register 2 is connected bit by bit with the same name groups, inputs of output register 6, group of elements I 7 and group

elements of comparison 13. The group of outputs (1 ... P) of output register 6 through adapter 23 is connected to a group (1 ... n) of device outputs, a group of outputs (1.1 ... 1.1) of adapter 23 is bitwise connected to a group of inputs the JB address counter, the output group (2.1 ... 2.1) of the adapter 23 is bitwise connected to the input group of the same name of comparison elements 15, the group of inputs (1 ... I) of which is bitwise connected to the same input group of the ROM 14 and outputs (1 ... I) of the address counter 8. Groups of outputs (1.1 ... 1.p) ... (K. 1 ... K, p) of adapter 23 are bitwise connected to the same name ppami input elements of comparator 13. The adapter 23, the control output is connected to a first input of the second AND gate

18 and with the input of the element HE 21, the output of which is connected to the first input of the third element AND 19, the second input of which is connected to the output of the first element OR 16, whose inputs are connected separately to the outputs of each comparison element of the comparison element group 13. The group of outputs (1 .. .P) ROM 14, the bit is connected to the second group of inputs (1 ... n) of the group of elements AND 7. whose output group (1 ... n) is bitwise connected to the group of inputs (1 ... n) of the adder 1 modulated. Outputs of the second 18 and third 19 elements AND

connected to the corresponding inputs of the second element OR 17, the output of which is connected to the inputs of the recording of the output register 6. The overflow output of the packet counter 20 is connected to the input input of the element

comparison 15 and through the second delay element 10 with the counting input of the address counter 8. The output of the sync clock generator is connected to the synchronous inputs of the driver of a single pulse 22 and the first element AND 4. The installation input is in the logical state

the flip-flop 3 is connected to the output of the reference element 15, the Setup input to the state of the logical unit of the trigger-3 is connected via the fourth element 12 to the output of the single pulse generator 22 and to the inputs of the zero shift register 2, the output register iS, counters of address 8 and package 20, as well as with the installation output to zero device. The output of the first element And 4 is connected to the counting input of the counter of the packet 20 through the first delay element 9 with the polling input of the group of comparison elements 13, the second input of the second element And 18 and the third delay element 11 with the third input of the third element And 19, as well as the synchronization output devices. Input Hyck device is connected to the same input shaper single pulse 22;

The binary sequence generator works as follows.

After connecting the Object (for example, a control object) to the outputs of the adapter 23 to the START signal, a single pulse shaper 22 opens and passes a single pulse pulse 2 to its output from a series of clock pulses of the generator 5, which reset the output register 6, the counter address 8 (recorded, start address code) packet counter 20 and through the output of the installation device to a zero object (if necessary). Then, through delay element 12, sets trigger one to logical state one. The initial state of the address counter 8 is determined by the start address (AH), protective in adapter 23. The recorded code, for example, with n 8 AI 00000001 from the outputs (1 .. .I) the address counter 8 is fed to the ROM 14, at the outputs (1 ... n) of which the following is established: information, which is the binary feedback polynomial of the shift register 2. For each clock pulse coming from the output of the AND 4 element, the shift register 2 forms at its outputs (1 ... n) a binary code representing a shift by one bit towards the higher bits of the contents of register 2 shift while simultaneously writing in its least significant bit (first) sums modulo two 1 and closed bits, i.e., open through AND 7.1 ... 7.P feedbacks of the shift register 2 connecting the corresponding outputs (1 ... P) register 2 shift with the same inputs (1 ... P) of the modifier 1 modulo two. Closed feedbacks are determined by a feedback polynomial — a binary code at the outputs (1 ... n) of ROM 14.

At the same time, for each clock pulse, the addition of 1 on the counter 20 of the packet is performed. After the delay time of element 9, a group of elements of comparison 13 is polled, each of which compares the binary code generated at the output of the shift register 2 at a given synchrotact with the code specified by the adapter 23 at the outputs (1, .. n) ... (K.1. ..K.p), which is a forbidden code for an object. Each prohibited p-bit code arrives at a group of inputs of elements of comparison 13.1 ... 13. n from the corresponding group of outputs of forbidden adapter codes 23.

5 The delay element 9 is chosen so that the interrogation of the elements 13.1 ... 13.k is carried out after completion of the generation of the next code at the outputs (1 ... n) of the shift register 2.

0 If the object does not have any forbidden codes, then the output of the control of adapter 23 is Level 1, which through the NOT 21 element locks the AND 19 element and opens the AND Sh element directly.

5 result, regardless of the operation of the group of elements of comparison 13, for each clock pulse through delay element 9. element AND 18 and element OR 17 is formed. Record impulse on the corresponding input

0 of the issuing register b, recording the next generated binary code at the outputs (1 ... n) of the register 2 shift through the same-named inputs (1 ... P) of the issuing register b into this register, from the outputs of which through

5 adapter 23, the next code arrives at the object, ect.

If the object has forbidden codes, for example, codes 11110011 and 00011001, then adapter 23 has a month at the control output. That is the level O, which through element 21 does NOT open the element AND 19 and locks the element 18. As a result, when it appears at the outputs (1 .. .p) register 2 shift one of the prohibited codes (any in any

5) the comparison output of the corresponding comparison element 13.1 ... 13.k is generated at the output of the comparison signal, which closes the AND 19 element through the OR 16 element to pass through

0 it is a pulse from the output of the delay element 11. In this case, the forbidden code is not written to the output register b and is not issued to the object. All the rest, except the forbidden codes, do not generate comparison signals on one of the comparison elements. 13.1 ... 13.k and do not change at the output of the OR element 16 level 1, which opens the element AND 19, passing the corresponding clock pulses from the output of the delay element 9 to the input of the output register 6

through the delay element 11 and elements And 19 and OR 17. Thus, all other codes arrive at the outputs of the device.

Let, for example, a certain control object be used as an object, for checking of which it is necessary to generate the following input actions in the specified sequence:

I10000000 2 11000000

301100000.

400110000

5, 10011000

611001100

701100100

800110010 /

900001100

1010000110

II11000011

1211100001

1311110000

 14 01111000

1500111100

1610011110

0000000111111001111000011001100000000

2nd forbidden code

This binary sequence contains all 27 binary codes that are required to test a given control object and, moreover, contains two stubble codes:

00011001 (after the 9th cycle) and

11110011 (after the 20th cycle), which, as described, are recorded in the adapter 23 and fed to the corresponding inputs of the Comparison Elements.

The generation process on a given feedback polynomial is completed when the packet counter 20 counts 2-1 synchrotacts, t. e. the highest possible package. If a shortened packet is used (as in the above example, since 29 2® is 1), then the shortened packet will be repeated several times (this is not harmful for testing the object, since it is equivalent to repeating the same test). After the overflow of the packet counter 20, a comparison element 15 is polled. When the start and end addresses coincide (as in the example in question, if the ANA "00000001 is taken) at the output, the comparison of the element 15 produces an end of work signal that resets logical zero trigger 3 and closes

The specified sequence is satisfied, for example, by a coding polynomial using 15 outputs of the second and eighth bits of shift 2 as working feedbacks (this is determined from tables or synthesized in advance on a computer for a specific given object), 00000001 in the ROM 14-20 the corresponding feedback control code is programmed to be 0100001. A binary sequence will be generated (the most significant bits to the right):

1 and prohibition initial code

element 4, stopping the supply of clock pulses and stopping the generation process. If more complicated generation is required, isolating not one, but many different coding polynomials (polynomials of octave relations), then the end address is chosen to AK 00000010, if generation is required on two different polynomials, then AK 00000011, if generation is required on three different polyemes, and etc., After the overflow signal from the counter of the packet 20, a comparison signal is not generated, and, through the delay element 10, the overflow signal adds 1 to the contents of the address counter 8 and generates the next address to access the ROM 14 for the considered romera:

one-....

AH + 1 00000010. In the second cell of the ROM 14, another feedback code is recorded for this purpose, with the help of which, as described, a similar, but already different, structure of test actions (other codes and their other ordering) is generated, allowing required testing of an object with a given completeness and with the exclusion of prohibited codes.

The proposed technical solution, due to the possibilities inherent in it, to promptly rebuild the encoding polynomial, i.e., change the structure and length of the generated binary sequence, as well as determine the length and composition of the generated binary sequence with any encoding polynomial, can form the composite binary sequences generated on several different coding polynomials, use also binary sequences in which there are no unwanted (forbidden from the point of view of numbers ovogo object control) binary combination, allows for a formal basis for synthesizing various digital exposure test individual objects; (simple or compound binary sequences), the most effective in each specific case - for each specific digital object. This way, it is possible to improve the completeness of testing digital objects with the minimum possible length of the test aggregate and, as a result, to increase the efficiency of monitoring and diagnostics of these objects.

Claims (1)

Claims: A binary sequence generator comprising a modulo-two modularly connected in series and a shift register, a trigger connected in series, and the first element AND, the second input of which is connected to the output of the clock generator, the first pulse counter, the first delay element, block: comparison, element OR, the second element is AND, the third element is AND, the first code of which is connected to the output of the element N €, register, the control input of the shift register is connected to the output of the first element AND, characterized in that. the purpose of expanding the functionality due to the possibility of changing the structure of the formed sequences, the group of elements AND, the second delay element, the third delay element, the fourth delay element, the group of comparison blocks, the memory block, the OR-NOT element, the second counting pulses are introduced into it , single pulse shaper, adapter and Start bus connected to the first input of a single pulse shaper, the output of which is connected to the first input of the shift register, to the first input of the register, to the first input the house of the first pulse counter, with the first input of the second pulse counter and with the input of the fourth delay element, whose output is central to the first trigger input, the second input of which is connected to the output of the comparator unit, the first group of inputs of which is connected to the output group of the first pulse counter and the group block inputs the memory, the outputs of which are connected to the first inputs of the corresponding elements AND of the group of elements AND, the second inputs of the elements AND of which are connected to the corresponding outputs of the shift register, with the first groups of inputs of the comparison blocks of the group of comparison blocks and with the group of inputs of the register whose outputs are connected to the inputs of the adapter, the first group of outputs of which is connected to the group of inputs of the first pulse counter, the second input of which is connected to the output of the second delay element, the input of which is connected to the output of the second pulse counter The second group of inputs is connected to the second group of adapter outputs, the output of which is connected to the input of the NOT element and the first input of the second element AND, the output of which is connected to the first input of the OR element, the second input of which is connected to the output of the third element And, the second entrance of which. connected to the output of the third delay element, the input of which is connected to the second input of the second element And, to the inputs of the comparison blocks of a group of comparison blocks and to the output of the first delay element whose input is connected to the second input of the second pulse counter and to the output of the first And element, the second input of which connected to the second input of the formate) 1 single pulse, the output of the element OR is connected to the second input of the register, the outputs of the elements AND of the group of elements I are connected to the inputs of the modulo two, the third input of the third element A and connected to the output of OR-NO element, whose inputs are connected to outputs of the comparison unit comparing a group of blocks, the second group of inputs of which are connected to respective outputs adapter groups. ShMZ-si-H2 T. from ЗЛ.6 25 on Sl.6 on mjs on 3Ji.f8,2f on 3.13.1 on 13.2