SU1709241A1 - Device for prestarting checking of capacitor capacitance - Google Patents

Abstract

The invention relates to a measurement technique, in particular to devices for the admission control of a capacitor capacitance. The purpose of the invention is to improve the accuracy of the tolerance control of the capacitance of capacitors by compensating the bias voltage. The device contains a source 1 of reference voltage ^ keys 2 and 3, a capacitor 4, an operational amplifier 5, a sampling-storage unit 6, a comparator 7. logical block 8, a register 9, a decoder 10, keys 11 and 12, a key 13, a capacitor 14, key 15, capacitor 16, condenser 17, control unit 18. 3 Fig. X »About SOGO1 ^

Description

The invention relates to a measurement technique, in particular, to devices for tolerance testing of the capacitance of electrical capacitors.

Known devices for tolerance control of capacitors.

The devices described in the author. Mg 894856 and 423054, contain a reference voltage source, capacitors, switches, an integrator, a sample-storage unit, a control device. The device described in auth. N: 894856, converts the difference in electric capacitances of the two capacitors into a code and into a pulse-width modulated signal. In the device described in auth. No. 423054, the tank is monitored to one side of the tolerance limit. All of these devices in the process of converting input values to the output implement an iteratively integrating method of conversion, so that with relatively simple and low requirements for the parameters of most of the blocks included in their composition, they have a rather high conversion accuracy. However, a common drawback of these devices is the error resulting from the presence of a bias voltage at the input of the operational amplifier. ,

The closest in technical essence is the device described in auth.St. No. 864185. This device contains a series of reference voltage source, the first and second keys, the first capacitor connected by the first plate to the first and second keys, the operating amplifier connected in series, the non-inverting input liOTOporb connected to the common bus of the device, the sampling-storage unit The output of which is connected to a comparator, a logic unit, a register and a decoder connected in series, the second input of the comparator is connected to the source of the reference voltage, the third and fourth keys, n Connected to the output of the sample-storage unit, the third key is also connected to the fifth key and the first plate of the second capacitor, and the fourth key is connected to the sixth key and the first plate of the third capacitor, the fourth capacitor connected by the first plate to the inverting input of the operational amplifier, the control unit, connected by the first output to the control input of the first key, the second output to the control inputs of the second, fifth and sixth keys, the third output to the input

control of the third key, the fourth output to the control input of the fourth key, the fifth output to the control input of the sampling-storage unit, the sixth output

- to the control input of the logic unit, and the seventh output - to the control input of the decoder. This device, as well as the device described above, implements an iteratively-integrating conversion method, which, given the comparative simplicity of the hardware implementation, provides it with a sufficiently high conversion accuracy. However, the presence of a bias voltage at the input of the operational amplifier introduces an error in the capacitor capacitance control. The conversion function of this device taking into account the bias voltage will be

Se

20

UBUX EO-UCM

The aim of the invention is to improve the accuracy of the tolerance control capacity

capacitors by compensating for the bias voltage of the opamp. The goal is achieved in that the first and second switches, the first capacitor connected by the first lining to the first and second keys, connected in series with the operating amplifier,

the non-inverting input of which is connected to the common bus of the device, the sample-storage unit whose output is connected to the comparator connected in series, the logic unit, the register and the decoder, the second comparator input is connected to the source of the reference voltage, the third and fourth keys connected to the output of the sampling unit- storage, the third key is also connected to the key and

the first plate of the second capacitor, and the fourth key is connected to the sixth key and the first plate of the third capacitor, the fourth capacitor connected by the first plate to the inverting input

an operational amplifier; a control unit connected by the first output to the control input of the first key, the second output to the control inputs of the second, fifth and sixth keys, the third output

- to the control input of the third key, the fourth output to the control input of the Fourth key, the fifth output to the control input of the sample-storage unit, the sixth output to the control input

logic block, and the seventh output - to the control input of the decoder, the seventh and eighth keys are additionally entered, the seventh key is connected to the inverting input and output of the operational amplifier, as well as to the first plate of the fourth capacitor and the second output of the control unit, and the eighth key is connected to the output of the operational amplifier, to the second plate of the fourth capacitor and to the second output of the control unit, with the second plates of the first, second and third capacitors connected to the inverting input The second amplifier, the second, fifth, and sixth keys are connected to the common bus of the device.

Figure 1 shows the structural scheme of the device proposed: Figure 2 shows the sample-storage unit; fig.Z - logical block.

The device for monitoring capacitor capacitance contains a source of reference voltage 1 in series, keys 2 and 3, a capacitor 4 connected by a first output to keys 2 and 3. a series-connected operational amplifier 5 whose non-inverting input is connected to the common bus of the device, sampling unit 6 storage, the output of which is connected to the serially connected comparator 7, logic block 8, register 9, decoder 10, the second input of the comparator 7 is connected to the source 1 of the reference voltage, keys 11 and 12, under Switched to the output of the battery selective block, the key 11 is also connected to the key 13 and the first lead of the capacitor 14, and the key 12 is connected to the key 15 and the first lead of the capacitor 16, the capacitor 17 is connected by the first lead to the inverting input of the operational amplifier 5, the control block 18, connected by the first output to the control input of the key 2, the second output to the control inputs of the keys 3.13 and 15, the third output to the control input of the key 11, the fourth output to the control input of the key 12, the fifth output to the control input of the block 6 sampling-storage the sixth output is to the control input of the logic unit 8, the seventh output is to the control input of the decoder 10, the keys 19 and 20, and the key 19 is connected to the inverting input and output of the operational amplifier, as well as to the first capacitor plate 17 and the output of the control unit 18 , and the switch 20 is connected to the output of the operational amplifier 5. to the second plate of the capacitor 17 and to the output of the control unit 18, the second plates of the capacitors 4, 14 and 16 are connected to the inverting input of the operational amplifier 5, and the switches 3, 13 and 15 are connected to common bus device twa.

As a control unit 18,

use a series-connected generator 21, a counter 22, a decoder 23, and, as a logical block B, a device shown in FIG.

The device works cyclically. Each cycle consists of alternate key closures. In the first cycle, the keys 3 are closed. 13 and 15,19, and the clutch 20 is opened. As a result, the operational amplifier 5 is transformed into a voltage follower, and the capacitors 4, 14 and 16 are charged before the bias voltage UCM at the input of the operational amplifier 5, the open switch 20 prevents the discharge of the capacitor (1c 17, Po

key 11 is closed to the second cycle. As a result, a voltage will be received at the inverting input of the operational amplifier 5

ALARM - UCM UcM Usbix.

The third clock closes the key 2 and, at the inverting input of the operational amplifier 5, according to the voltage

Ео - UCM + and

JCM

where UBHX is the voltage at the output of sampling-storage unit 6, UCM is the bias voltage of the operational amplifier 5;

EO is the reference voltage. In the fourth cycle, the storage and storage of the output voltage of the operational amplifier 5 is stored and stored in block 6, provided that the duration of the clock signals is much longer than the constant charging time of the capacitors 4, 14 and 16 and after a large number of

cycles at the output of block 6 sample storage is set voltage

V l2-2 cl4

50

. Where C4 is the capacity of the controlled capacitor 4:

Ci4 - capacitor capacitance 14.

The control unit 18 sets the duration. iterative process (sets the number of cycles, controls the keys and the block-storage unit). IF V., Eo. then the comparator 7 is activated and the logical block 8 writes to the register 9 the logical

1. If V EO, i.e. comparator 7 does not work, then O is written. The comparator works if C4 See and does not work if Ci4 C / j. After the result of comparing the capacitances C4 and C is recorded in the register 9, the control unit 18 resumes the iteration process, and the capacitor 16 switches instead of the capacitor 14. After the end of the iteration process, the duration of which is set by the control unit 18, the output voltage of the sampling unit 6 - storage is defined by the expression

V. E

Next, the voltage V; -, Ha of the comparator 7 is compared with the voltage Eo of the source 1 of the reference voltage. If 4v Eo (which is equivalent to C4 Cie). then the comparator 7 is triggered and the logical block 8 writes logical 1 to register 9. After this, the control block 18 gates the decoder 10 and the output of the TO decoder displays information about the capacitor under study. If the capacitance of the capacitor 14 is chosen equal to the lower limit of the allowable value of the capacitors under study, and the capacitance of the capacitor 16 is chosen equal to the upper limit, then if the information corresponding to two logical 1 is written in register 9, the capacitance value of the capacitor under investigation goes beyond the tolerance limits to the lower and upper parties. If information 1, O is recorded in register 9, then the Norm signal appears at the corresponding output of the decoder 10. This device does not require the use of an op amp with a small bias voltage, and therefore a low cost op amp can be used.

The advantages in accuracy of control of this device over the prototype are as follows: The prototype

Uaux EO -I- UCM})

If you take an operational amplifier 544UD2A. having a temperature drift of 50 µV / ° C, and the temperature change will be, Eo 0.1 V

50 10 30

 100% 1.5%

At 0.1

If we also take into account the time drift, the error will increase.

Introduction to the device two keys with the appropriate connections allowed

improve the accuracy of tolerance control capacitors. As a result, due to the increase in accuracy, the proposed device can be used instead of a digital capacitance meter in the composition

0 high-frequency automated control system, which is more expensive in comparison with the proposed device, which made it possible to simplify and cheapen the automated system, as well as

5 to increase its reliability.

Claims (1)

The invention The device tolerance control capacitance containing serially connected source of 0 voltage, the first and second keys, the first capacitor, the first output of which is connected to the second output of the first switch, a serially connected operational amplifier, the non-inverting input of which is connected to a common bus, a sampling-storage unit, a comparator, a logic unit, a register and a decoder, the second the input of the comparator is connected to the source of the reference voltage, the third and fourth 0 keys, the first terminals of which are connected to the output of the sampling-storage unit, the second terminal of the third key is connected to the first terminal of the fifth key and the first terminal of the second capacitor, the second terminal of the fourth key is connected to the first terminal of the sixth key and the first terminal of the third capacitor, the second terminals of the first , the second and third capacitors are combined and connected to the first output of the fourth 0 of the capacitor and the inverting input of the operational amplifier, the control unit, the first output of which is connected to the control input of the first key, the second output to the control inputs of the second, fifth and sixth keys, the third output to the control input of the third key, the fourth output to the control input of the fourth the key, the fifth output — with the control input of the sampling-storage unit, the seventh output — with the control input of the decoder, the sixth output — with the controlling input of the logic unit, in order to improve the accuracy tively introduced the seventh and eighth th keys, and 5, the first terminal of the seventh key is connected to the inverting input of the operational amplifier, the first terminal of the eighth key is connected to the second output of the fourth capacitor, the second terminals of the seventh and eighth keys are connected and connected to the output of the operational amplifier, the control inputs of the sixth and seventh keys are connected to the second output of the control unit , the second terminals of the second, fifth, and sixth keys are connected to the common bus. H5L.5 . i8 Fig.Z FIG. 2