SU1700274A1 - Gas-turbine engine vibration limiter - Google Patents

Abstract

The invention relates to the field of automatic control and monitoring of the CCD, in particular, to devices for limiting vibrations, and makes it possible to increase the efficiency of control of the CCD. The limiter contains a vibration sensor 1, a filter 2, an alternating voltage constant-voltage converter 3, an amplitude discriminator 4, a tachometric signaling device 5, circuit AND 6, circuit OR-NOT 7, circuit AND-HE 8, memory block 9, threshold setpoint 10 level, sources 11 of the reference voltage, control unit 12, failure unit 13, external control start bus 14, installation bus 15 and delay unit 16. The delay unit 16 allows generating a control start signal when the amplitude discriminator issues a signal about exceeding the permissible vibration in the time interval between successive starts of the control, delaying the predetermined time and allowing the signal about exceeding the permissible vibration to be output only according to the results of the amplitude discriminator and checking the output of the amplitude discriminator signal of exceeding the permissible vibration in the event of an amplitude discriminator malfunction. Such an embodiment of the limiter allows increasing the reliability of its operation. 5 il.

Description

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The invention relates to the field of automatic control and monitoring of gas turbine engines (GTE), in particular, to devices for limiting vibrations.

The purpose of the invention is to increase the reliability of the limiter.

FIG. 1 shows the structural scheme of vibration limiter; in fig. 2 is a block diagram of the threshold level setter; in fig. 3 is a block diagram of the control unit; Fig. 4 shows block diagrams of a memory unit, a failure unit, a delay unit and their connections; in fig. 5 is a timing diagram of the operation of the limiter at the time when the amplitude discriminator triggers and issues a signal that the permissible vibration is exceeded.

The vibration limiter of a gas turbine engine (Fig. 1) contains a vibration sensor 1 connected in series, a filter 2, an alternating voltage constant-to-voltage converter 3 and an amplitude discriminator 4, a tachometer signaling device 5, the circuit AND 6, the circuit OR NOT 7, the circuit AND-NOT 8, memory block 9, threshold level adjuster 10, reference voltage sources 11, control unit 12, failure unit 13, external control start bus 14 and installation bus 15 connected to the first inputs of memory block 9, failure unit 13 and circuits And 6, the second input is the last connected the first output of the tachometer indicator 5, the second output of which is connected to the first input of the control unit 12, the second input of which is connected to the external control start bus 14, the first output of the amplitude discriminator 4 is connected to the second inputs of the memory unit 9 and the failure unit 13 and the first input The AND-NE 8 circuit, the output of which is connected to the first input of the OR-NOT 7 circuit, the output of which is connected to the third input of the AND 6 circuit, the output of memory block 9 is connected to the second input of the OR-NOT circuit 7 and the first input of the threshold level setpoint generator 10, second entry last The one is connected to the second output of the amplitude discriminator 4, and the third to the output of sources 11 of the reference voltage, the first output of control unit 12 is connected to the third inputs of memory block 9 and the failure unit 13, the fourth input of the latter is connected to the second output of control unit 12, the third the output of which is connected to the fifth input of the failure unit 13 and the fourth input of the memory unit 9, and the fourth to the fourth input of the unit 10 of the threshold level and the sixth input of the failure unit 13. In addition, the vibration limiter contains a delay block 16, the first output of which is connected to the fourth

the input of the circuit is AND 6, the second to the second input of the circuit IS-NOT 8, and the third to the third input of the control unit 12, the first input of the delay unit 16 is connected to the installation bus 15,

the second to the fifth output of the control unit 12, the third to the output of the failure unit 13, the fourth to the first output of the amplitude discriminator 4, the fifth to the sixth output of the control unit 12, and the sixth to the seventh output of the control unit 12, the sixth output which is connected to the fifth input of memory block 9.

The threshold level setting device 10 (FIG. 2) can be made in the form of a key control circuit 17, resistive motors 18 and keys 19.

The control unit 12 (Fig. 3) can be made in the form of keys 20, the first trigger 21, the first pulse counter 22, the output decoder 23, the generator 24, the OR element 25, the second pulse counter 26, the delay element 27, the second trigger 28, controllable delay element 29 and third trigger 30.

5Block 9 of memory (FIG. 4) may be made in the form of an AND 31 element, an OR 32 element, a trigger 33, and an NAND element 34.

Block 13 failure (Fig. 4) may be made in the form of the element OR 35, the element

0 NOT 36, trigger 37, elements AND-NOT, NOT, AND-NOT and NOT 38, 39, 40 and 41, trigger 42.

The block 16 of the delay (Fig. 4) can be made in the form of the element 43 of the delay, the elements of NAND, OR, and NOT 44-46 trigger 47,

5 elements OR NOT 48, shaper 49.

FIG. 5 shows the graphs 50-64 signals, respectively, on the bus 15 of installation O, the first input of the amplitude discriminator 4, the output of the discriminator 4.

0 the output of the delay element 43, the output of the generator 49, the first output of the control unit 12, the fifth output of the control unit 12, the fourth output of the control unit 12, the output of the HE element 39, the second

5 the output of the control unit 12, the output of the memory unit 9, the seventh output of the control unit 12, the first output of the delay unit 16, the third output of the control unit 12, the output of the AND 6 circuit.

0 Amplitude discriminator 4 is a threshold device, the output of which varies from logic level O to logic level 1. when the magnitude of the voltage

5, the first input exceeds the voltage value at the second input.

The signal control unit 12 from the external control start bus 14 or from the tachometer indicator 5 or from the delay unit 16 generates control signals that are supplied to the memory unit 9, the threshold level setter 10, the failure unit 13, the delay unit 16 and provide the performance check amplitude discriminator 4. If control unit 12 is faulty, then a fault signal is generated at its sixth output, which is fed to memory unit 9, delay unit 16 and to the output of the limiter to signal a malfunction.

Failure unit 13 is designed to generate a device failure signal in the event that an amplitude discriminator 4 detects a malfunction during performance monitoring.

With a serviceable device in order to prevent false triggering of the trigger 42, for example, from short-term interference and, consequently, giving them a false signal of a device failure, the output of the element HE 39 is connected to the outputs of the elements AND-HE 38, AND-HE 40, to j-input of the trigger 42 and to the input element NO 41, the output of which is connected to the K-input of the trigger 42 (Fig. 4).

In the intervals between successive runs of the health control from the fourth output of the control unit 12, the signal in the form of logical 1 is fed to the input of the HE element 39 (Fig. 4, Fig. 5c, chart 57,), the output signal of which is in the form of a logical O in the above intervals time allows you to maintain the initial state of the trigger 42 when exposed to interference.

The delay unit 16 is designed to delay the generation of a signal that the permissible vibration level is exceeded for a predetermined time and to generate a start signal for the control unit 12.

The delay element 43 (Fig. 4) is a counter-adder, the output trigger of which is triggered and self-blocked when a certain number of pulses arrive at the counter input, for example, from the generator 24 output of the control unit-12 (not shown). The operation of the counter is permitted only with the presence of a resolution signal in the form of a logical 1 on the first and second inputs of the delay element 43 connected respectively to the first output of the amplitude discriminator 4 and to the bus 15 of installation O (Fig. 4). In this case, after a predetermined time at the output of the delay element 43, a signal is established in the form of a logical 1, which permits the normal operation of the NAND circuit 8 and the driver 49 of the delay block 16 (Fig. 4).

If at the first output of the amplitude discriminator 4 or on the bus 14 of installation O a signal is set as logical O, then the counter-adder is set to 5 the initial state and the output of delay element 43 sets the signal as logical O. This signal goes to the second inputs of the circuit AND-NOT 8 and shaper 49 block 16 delay and blocks them

10 work.

The first output of the amplitude discriminator 4 through the first input of the OR element 45, and the bus 15 of the installation O through the second input of the element OR 45 are connected to the R-input of the trigger 47 of the delay block 16 (Fig. 4). Therefore, in the presence of a signal in the form of a logical O on the first output, the amplitude discriminator 4 or on the bus 15 of the installation O, the trigger 47 is set to the initial

0 state. At the same time, the output Q of the flip-flop 47 sets the signal as logical 1. This signal is applied to the first inputs of the driver 49 and the element OR-48, inverted by the element IL AND-NOT

5 48 and from its output in the form of a logical O it is applied to the second input of the circuit AND 6 and prohibits other signals from passing through its remaining inputs.

When a signal arrives at the first input of formatter 49 as logical 1, other signals are allowed to pass through its remaining inputs.

The prohibition signal from the fifth output of the control unit 12, arriving at the third

5 the input of the delay element 43 and the element OR 45 (FIG. 4) and acting during the health check as a logical O (FIG. 5, graph 56, te-ti2), blocks the passage to the delay element 43 and the trigger 47

0 sIRnal in the form of a logical O from the first output of the amplitude discriminator 4 during the health check, which allows to keep the output signal level during the health check

5 delay element 43 and trigger 47 (before the signal arrives from the seventh output of control unit 12) such as the level of this signal was before the start of the health check.

0 The first three inputs of the imager 49 of the delay block 16 are connected respectively to the outputs of the delay element 43, the trigger 47 of the delay block 16, the trigger 42 of the failure block 13 (FIG. 4), and the fourth input f

5, the driver 49 is connected to the output of the generator 24 of the control unit 12 (not shown). If there are signals in the first three above-mentioned inputs of the signal maker 49 in the form of logical 1 from its output, pulses with a frequency of the generator 24 are sent to one of the inputs of the keys 20 of the control unit 12 (Fig. 3) and start the last one. The presence on any of the first three above inputs of the imager 49 of the signal in the form of a logical O stops the passage of the pulses of the generator 24 through the fourth input of the imager 49 of the delay block 16 and coming from the output of the latter to the launch of the control block 12.

The vibration limiter works as follows.

After switching on the supply voltage of the signals of the bus 15 of the installation O (Fig. 5, graph 50), the control unit 12 (not shown), the memory unit 9, the failure unit 13 and the delay unit 16 are reset.

In the initial state, the signals are given:

from the output of memory block 9 to the first input of the setting device 10 of the threshold level and the second input of the OR-NOT 7g circuit

from the fifth output of the control unit 12 (Fig. 4 and 5, schedule 56) to the second input of the delay unit 16;

from the fourth output of the control unit 12 (Fig. 4 and 5, schedule 57) to the fourth input of the threshold level setting device 10 and the sixth input of the failure unit 13;

from the third output of the control unit 12 (Fig. 4 and 5, plot 63) to the inputs of the memory unit 9 and the failure unit 13;

from the output of the failure unit 13 to the third input of the delay unit 16, signals are given in the form of logical 1, which enable the operation of the above schemes;

From the second output of the delay block 16 to the second input of the AND-HE8 circuit (Fig. 4 and 5, schedule 53) and from the first output of the delay block 16 to the fourth input of the And 6 circuit (Fig. 4 and 5, chart 62), the signal is given as logical O, which prohibits the passage of signals through their other inputs.

At the same time, the installation signal O (Fig. 1 and 5, plot 56,) also enters the first input of circuit 6 and prevents it from tripping, thus preventing it from issuing a false signal at the moment the power is turned on.

After the installation signal has been terminated (Fig. 5, Schedule 50), the GTE vibration limiter is reset and ready for operation.

The signal is in the form of alternating voltage with a frequency of vibration, the magnitude of which is proportional to the vibration level of the gas turbine engine casing and varies both in amplitude and frequency from the output of vibration sensor 1 through filter 2 of a controlled frequency range and through converter 3

AC voltage is supplied to the first input of the amplitude discriminator 4 and simultaneously to the output of the device for recording the value of the converted DC voltage (analog signal, Fig. 1), for example, in the recorder. When the vibration level in the controlled frequency range does not exceed the allowable level, the voltage level at the first input does not exceed the voltage level at the second input of the amplitude discriminator 4 (Fig.) And from its first output the signal, for example, in the form of a logical O, enters the block inputs 9 memories,

block 13 failure, block 16 delay and the circuit IS-NOT 8. From the output of the circuit IS-NOT 8, the inverted signal in the form of logical 1 is fed to the first input of the circuit OR-NE 7, to the other input of which from the moment of feeding from

the output of memory block 9 also receives a signal in the form of a logical one. Then, from the output of the OR-NOT 7 circuit, a logical O is fed to the third input of the AND 6 circuit, to the fourth input of which a signal arrives

the form of logical About with the first output of block 16 delay. On the second and first inputs of the circuit AND 6 from the output of the tachometer alarm 5 and through the bus 15 of the installation O after turning on the power and increasing the speed

The engine, up to a certain level, receives signals in the form of a logical 1, thereby permitting the passage of other signals through this circuit to its other inputs. The presence of a signal in the form

logical O on any of the inputs of the circuit And 6 does not trigger the last one, and therefore the actuator (conventionally not shown in the drawing).

If, during engine operation, the vibration level begins to increase and exceeds the allowable one, then the voltage level 11 in 1 at the first input of the amplitude discriminator 4 also increases and begins to exceed the preset level

the voltage Uex2 at its second input (Fig. 4 and 5, plot 51, t ti) and the amplitude discriminator 4 is triggered (Fig. 5, plot 52, ti). From the first output of the amplitude discriminator 4, the signal that the permissible vibration level is exceeded in the form of a logical 1 is fed to the inputs of the circuit EH E 8, memory block 9, failure block 13 and delay block 16.

The output signals of memory block 9 and

5 of the fault unit 13 does not change their state, since the blocks only operate during the performance monitoring process.

The output signals on the first, fifth and fourth outputs of the delay block 16 (FIG.

4 and 5, the charts 52, 53, 54 and 62, p) do not change their state, since:

the trigger 47 remains in the initial state, therefore at the fifth output of the control unit 12 there remains a signal in the form of a logical

at the output of the delay element 43, the initial state signal is stored, i.e. in the form of a logical

operation of the driver 49 is prevented by a signal in the form of a logical O from the output of delay element 43.

Therefore, the inputs of the circuit And 6 receives signals in the form of a logical O and it does not work.

If at the first output of the amplitude discriminator 4 the signal continues to remain as logical 1, then after a predetermined time of the EPES, for example, after 2-3 seconds, the output of delay element 43 sets the signal as logical 1 (Fig. 5, plot 53, t2 ). This signal is applied to the inputs of the AND-HE circuit 8 and driver 49 (Fig. 4). The circuit AND-NOT 8 is triggered, its output signal in the form of a logical O is inverted by the circuit OR-NOT 7 and in the form of a logical 1 is fed to the input of the circuit AND 6. The circuit AND 6 does not work, as its input from the output of the delay block 16 continues to flow a signal in the form of a logical O (Fig. 5, plot 62, ta).

The signal in the form of logical 1 to the second input of the imaging unit 49 triggers the latter. At the output of the imaging unit 49, a control start signal is generated (Fig. 5. Schedule 54, t2-ta, which is fed to one of the inputs of the keys 20 of the control unit 12 and starts the last one, as a result of which control signals are generated at the outputs of the unit 12 (Fig. 3, 4 and 5, plots 55, 56, 57, 59, 61 and 63).

On the memory signal (Fig. 5, graph 55,) from the first output of the control unit 12:

trigger 33 of memory block 9 remembers the output signal level of amplitude discriminator 4 as logical 1. This signal is inverted by AND-NOT 34 element and from its output as logical O is fed to the second input of the OR-HE circuit 7, which ensures the same health at its output signal in the form of a logical 1, despite the change in the level of the signal at its first input (Fig. 5, ts-tia);

the trigger 37 of the failure unit 13 memorizes the output signal level of the amplitude discriminator 4 as logical 1. Therefore, the output Q of the trigger 37 sets the signal as logical 1 and is fed to the second input of the AND-HE element 38 and at the output Q - as logical O and is applied to the second input of the element AND-NOT 40. 5 The prohibition signal from the fifth output of the block

Control 12 with a logic level O operates during a period of time (FIG. 5, graph 56) and is applied to the third inputs of the delay element 43 and the OR element 45 of the delay block 16, prohibiting the passage through the other inputs during the above monitoring period a signal with a logic level O from the first output of the amplitude 15 discriminator 4, therefore, the output signals of the delay element 43 and 45 or 45 in the time interval become logical 1.

Control signal from the fourth output

0 control unit 12 with a logic level

About valid in the time interval te-tg

(Fig. 5, chart 57) and enters the second

input setpoint 10 threshold level and on

the input element NO 39 of the failure unit 13 (FIG.

5 4).

Prior to the input of the element HE 39, a signal with a logic level O at the output of the latter (FIG. 5, graph 58, t te), a signal was set with a logic level O, which prevented the flip-flop 42 from being reset, under the influence of interference, into the false signal state Failure, which would prohibit the work of the former 49 block 16 delay. After submission of 5 to the input element HE 39 of a signal with a logic level O, the output of the latter is set to a signal with a logic level 1, however, since the output of the element HE 39 is connected to the outputs of the elements AND- 0, NB 38, AND-NOT 40, the level The output signal of the specified outputs in the time interval will depend on the state of the input levels of the elements AND-NOT 38 and AND-NOT 40.

5 According to the control signal (Fig. 5, graph 54), which enters the input of the key control circuit 17 of the setting unit 10 of the threshold level (Fig. 2), if there is a signal at its first input with a logic level O c 0 of the output of the memory block 9 key management is triggered by means of keys 19, resistive dividers 18 and sources 11 of reference voltage (fig. 2), at the output of unit 10 of threshold level, output a high level signal (for example, 7 V), which is fed to the second amplitude input discriminator 4 (Fig. 5, graph 51). The level UsT.7 V ensures that the amplitude discriminator 4 is turned off even at

a signal at its first input, corresponding to the maximum permissible vibrations, for example, 1) pre-vibration 6.3 V,

The amplitude discriminator 4, if it is operational, at the moment of time te switches and a signal in the form of a logical O is set at its first output (Fig. 5, graph 52, te-tg). This signal is applied to the inputs of the NAND 8 circuit, the memory block 9, the failure block 13, the delay block 16.

The AND-HE circuit 8 in the time interval te-tg is triggered and at its output a signal is set as logical 1, which is fed to the input of the circuit IL-AND 7. However, at the output of the latter, the signal continues to remain as logical 1, since the second input continues to signal as logical O from the output of memory block 9.

The memory block 9 does not work, since it can only be triggered during the action of the memory signal (Fig. 5, plot 60).

In block 16, delays: delay element 43, OR 45 do not work, since a prohibition signal is given to their inputs;

trigger 47 does not fire and is in the initial state, since the output signal has not yet arrived. Therefore, from the first output of block 16 to the fourth input of the circuit And 6, the signal continues to arrive in the form of a logical

driver 49 continues to operate, but its output signals do not affect the operation of control unit 12.

In block 13 of the failure, an AND-HE element 38 is triggered and at its output, connected to the outputs of the HE 39, AND-NO 40 elements, the input of the trigger 42 and the input of the HE element 41, the signal is set as logical O, since the first input of the element AND-NOT 38 from the output of the element 36 is at this time supplied a signal in the form of a logical 1, and to its second input a signal in the form of a logical 1 from the output Q of a flip-flop 37 (Fig. 4).

In the time interval, the input T of the trigger 42 of the failure unit 13 from the second output of the control unit 12 receives a failure signal (Fig. 4 and 5, schedule 59). Since in the time interval te-tg, the input j of the flip-flop 42 sends a signal as logical O, and the input K receives a signal with the level of logical 1 at the output of the NOT 41 element, after the influence of the failure signal of the flip-flop 42 wherein, at its output Q, a signal is set as logical O, and at output Q, with a logic level of 1, i.e. the output signal level corresponds to the initial state, as well as after the impact of the setting signal O. The signal from the output Q with the logic level 1 is fed to the second input of the AND-NOT element 44 and the third input of the driver 49 of the delay block 16 (Fig. 4), allowing them to be normal functioning.

At the moment of time tg, the action of the control signal (Fig. 5, diagram 57) stops;

0 10 threshold level is turned off, turning off and keys 19, the signal level at the output of the setpoint generator 10 of the threshold level returns to the initial, preceding control state. Therefore

5, the amplitude discriminator 4 is triggered and a signal is set at its output with a logic level 1 (Fig. 5, plot 52, tg), i.e. the same as before the health check.

0 In the time interval tio-tn from the seventh output of control unit 12 (FIG. 5, graph 61), an output signal is applied to input T of trigger 47 of delay unit 16 (FIG. 4), since the first and second inputs

5, the AND-NE element 44 is supplied at this time with a logic level 1 respectively from the first output of amplitude discriminator 4 and from the output Q of the flip-flop 42 of the failure unit 13, then after the effect of the output signal at the output Q of the flip-flop 47 of the delay 16 the signal is set to level -. logical O. This signal is applied to the first input of the element OR NOT 48, is inverted last and as a signal with

5 level logic 1 is fed to the input of the circuit And 6.

Circuit AND 6 is triggered and a signal is set at its output in the form of a logical 1 (Fig. 5, plot 64). This signal can

0 applied to the key that is triggered, turns on the actuator (not shown).

After triggering 47, the signal from its output Q with a logic level O

5 is applied to the first input of shaper 49 and prohibits its operation (Fig. 4).

At time ti2, the inhibit signal (Fig. 5, graph 56) is terminated, but this does not cause the output signals of the delay element 43 and the OR 45 block of the delay block 16 (Fig. 4) to change, since at both inputs of these elements time set signals with a logic level of 1.

5 In the interval from the third output of the control unit 12 (Fig. 5, graph 63), the control end signal with a logic level O and the trigger 33 of the memory block 9 and the trigger 37 of the block 13 are fed to the inputs of the memory block 9 and the failure block 13 of failure

are set to the initial state, as well as after the signal of the O installation,. In this case, the output of memory block 9 to the inputs of the OR-NOT 7 circuit and the setpoint generator 10 of the threshold level is signaled as logical 1, which does not interfere with their operation. Resetting the trigger 37 to the initial state does not cause a change in the initial state of the trigger 42 of the failure unit 13 (Fig. 4).

At this point, the limiter performance monitoring cycle is over, and the vibration limiter issues a signal that the permissible vibration is exceeded, is ready for further work and for repeating the performance monitoring.

Thus, the signal of exceeding the permissible vibration of an activated and healthy amplitude discriminator and, in case of a healthy device, is output by the Andb circuit:

after a delay due to the delay time (te d) of the delay element 43 and the time from the start of the health check until the trigger 47 is triggered by the delay block 16;

only after starting and performing a performance check, which is started by shaper 49 of delay unit 16 during the signal that the permissible temperature is exceeded by the amplitude discriminator 4.

If the amplitude discriminator 4 at the time ti worked and its signal was set to logical 1 (Fig. 5, graph 52) at its first output due to the faulty amplitude discriminator 4, the start of the health monitoring and operation of the limiter to the time period is performed as described above .

At time te from the output of the setting device 10 of the threshold level, the second input of the amplitude discriminator 4 is given a signal and VH23PU 7 V (Fig. 5, graph 51), however, the amplitude discriminator 4 does not turn off due to a malfunction and in the time interval at its first output the signal continues remain the same, i.e. in the form of a logical 1.

Because of this, the first input of the element IS-HE 38 in the gap te-tg from the output of the element 36 (Fig. 4) is given a signal with a level of logic O and the output of the element IS-HE 38 is set to a signal with a level of logic 1. A similar signal it is also set at the outputs of the elements HE 39, AND-HE 40. Therefore, after the impact of the failure signal (FIG. 5, graph 59), the trigger 42

the failure unit 13 is set to a state in which at its output Q a signal is set as logical O, i.e. trigger 42 is set to issue a 5 Fail signal. This signal, in the form of a logical O, is applied to the second input of the NAND 44 element, the third input of the imaging unit 49 of the delay unit 16 (FIG. 4) and the output of the device (not shown), signaling an amplitude discriminator 4 malfunction. Input to the third input of the imaging unit 49 signals with a logical level of O forbids its operation.

After exposure to the delivery signal (FIG.

5 5, the graph 61, tio-tii) the trigger 47 of the delay block 16 (FIG. 4) is set to a state in which a signal in the form of a logical 1 is set at its output, i.e. trigger 47 remains in the original as after

0, the signal of the set O, the state and the second input of the circuit And 6 continues to receive a signal in the form of a logical O, which prohibits the latter from tripping. Thus, if in the time interval between successive runs of the performance control, a malfunction of the amplitude discriminator 4 occurred and he began to give a false signal that the permissible vibration level was exceeded,

0 then the launch and performance monitoring of the amplitude discriminator prevents the device from issuing a false signal that the permissible vibration is exceeded and at the same time

5 allow to signal a malfunction.

If at this time on the bus 14 external

start control or from the output of the tachometer alarm 5 to one of the inputs

the control unit 12 receives the start-up signal of the 8th control, then the operability check of the amplitude discriminator 4 will be performed as described above and the amplitude discriminator 4 will again be confirmed.

5 Under the influence of random interference, the trigger 47 of the delay unit 16 will remain in the initial state, which additionally ensures that the device does not produce a false signal exceeding

0 permissible vibration.

If, under the influence of random interference, the trigger 42 of the failure unit 13 is reset, since from the output of the element HE 39 to the input of the j-flip-flop 42 is fed

5 signal with a logic level O, and the input K with a logic level 1 (Fig. 4), then the And 6 circuit does not give a false signal about exceeding the permissible vibration due to the fact that from the output of block 16 there is a delay (from the output of trigger 47, which is in its original state)

the input of the circuit And 6 continues to receive a signal with a level of logical O.

However, resetting the flip-flop 42 of the block 13 to the initial state removes the prohibition of the operation of the shaper 49 of the delay block 16 and the latter generates a control start signal. The control unit 12 is triggered and the operability of the amplitude discriminator 4 is performed, as described above. As a consequence, the flip-flop 42 of the failure unit 13 after the failure signal actions will again be set to the Fault output state, and then everything will happen as described above.

Thus, the return of the flip-flop 42 of the failure unit 13 to the initial state during the issue of the failure signal does not lead to the passage of a false signal from the faulty amplitude discriminator through the AND 6 circuit.

If the amplitude discriminator 4 is healthy and at the time ti began to give a signal that the permissible vibration rates were exceeded (Fig. 5, graph 52), then, as indicated above, through the time of ge backwards, the delay unit 16 will generate a health control start signal that goes on one of the inputs of the keys 20 of the control unit 12 and launches the latter. If the control unit 12 is faulty, a malfunction signal appears at its sixth output, for example, in the form of a logical O, which is applied to the second inputs of the AND-NE elements 34 of the memory block 9 and the OR-NOT 48 element of the delay block 16 (Fig. 4) and the output of the proposed vibration limiter to signal the malfunction of the control unit 12 (not shown) and the limiter as a whole.

The input to the second input of the element AND-NAND 34 of the signal memory block 9 is logical. It triggers the response and at its output sets the signal as logical 1, which is fed to the second input of the OR-NOT circuit 7 and does not interfere with its normal operation.

When a signal is fed to the second input of the OR-NOT 48 signal as logical O, a signal is set at its output as logical 1, which is fed to the fourth input of the AND 6 circuit and allows the signals to pass through its remaining inputs.

Since from the moment of time t2 (fig. 5, graphs 52 and 53), the signals of logical 1 are sent to both inputs of the AND-HE element 8, the output of the signal is set as logical

An O which is inverted by the element OR-NOT 7 and in the form of a logical 1 is fed to the third input of the circuit AND 6.

Due to the fact that at all inputs of the circuit

And 6 signals are sent in the form of logical 1, then the AND 6 circuit is triggered and, from its output, the signal on exceeding the permissible vibration level is applied to the output of the limiter, for example, to a key and an actuator (not shown).

Thus, in the event of a failure of the control unit 12, a signal that the permissible vibration level is exceeded appears at the output of the limiter through time

Gazad without testing the amplitude discriminator 4.

If delay element 43 is absent in delay block 16, then a health check will be started in

the time when the amplitude discriminator 4 produces a signal that the permissible vibration level is exceeded and the delay in outputting this signal will be determined by the time period t2-tn (Fig. 5, plots 54-61). For

To ensure the operation of the vibration limiter of the CCD in this case, the signal from the first output of the amplitude discriminator 4 must be sent to the second input of the driver 49 instead of the output of element 43

delays, and the second input of the NANDI circuit 8 is connected to the fifth output (prohibition signal) of the control unit 12 (instead of the output of the delay element 43, Fig. 4), as done in the known vibration limiter.

If the vibration level decreases at time W, and at time tis becomes a predetermined value below the permissible value, the amplitude discriminator 4 is turned off and a signal in the form of a logical O is set at its first output (Fig. 5, graphs 51, 52).

As a consequence, the output of the delay unit 43 of the delay unit 16 is set to a signal in the form of a logical O, which is fed to the second input of the imaging unit 49 and the AND-NOT circuit 8, prohibiting the operation of this circuit, and from its output the signal inverted by the OR-7 circuit the form of logical o is served

on the third input of the circuit And 6, prohibiting work on its other inputs.

When a signal is applied to the second input of the imager 49 in the form of a logical O, operation of the imager 49 is prohibited (Fig.

5 4);

through the OR element 45 is applied to the input R of the flip-flop 47 of the delay block 16 and sets the latter to the initial state (FIG. 4) and through the OR-NOT 48 element to the fourth input of the AND 6 circuit, prohibiting its operation, i.e. The GTE vibration limiter is reset.

The operation of the vibration limiter of the CCD with the performance monitoring, when the comparator is in good condition, and the signal that the permissible vibration level is not exceeded, is performed as follows.

In this case, prior to monitoring the operation, from the first output of the amplitude discriminator 4 to the inputs of the memory block 9, the failure block 13, the delay block 16 (FIG. 4), a signal is received in the form of a logical O, which does not cause the said blocks to operate. state (Fig. 4).

At the same time, this signal through the circuits AND-NOT 8 and OR-NOT 7 is fed to the third input of the circuit And b and prohibits its operation.

On the memory signal (Fig. 5, graph 53) from the first output of the control unit 12:

trigger 33 of memory block 9 remembers the output signal level of amplitude discriminator 4. At the same time, from output Q of trigger 33, the signal as logical 0 is inverted by AND-HE element 34 and from the last output as logical 1 and fed to the second input of the OR-NOT 7 circuit (Fig. 4);

the trigger 37 of the failure unit 13 stores the output level of the amplitude discriminator 4. At the same time, from the output Q, the second input of the AND-38 element is signaled as logical O, and the second input of the AND-40 element - as logical 1.

The prohibition signal (Fig. 5, graph 56) from the fifth output of the control unit 12 permits the operation of the delay element 43 and prohibits the passage of signals through the first and second inputs of the OR 45 element of the delay block 16 (Fig. 4).

On the control signal (Fig. 5, schedule 57) from the fourth output of the control unit 12:

through the element 39, the operation of the elements AND-HE 38 and AND-NO 40 of the failure unit 13 is permitted (Fig. 4);

The threshold level adjuster 10 generates a signal, for example, minus 0.1 V, which from the output of the latter is fed to the second input of the amplitude discriminator 4. The latter is triggered and at its output a signal is set as logical 1, which is fed to the first inputs of the AND-HE circuit 8 , memory block 9, failure block 13, and delay block 16.

The scheme AND-NOT 8 does not work, because at its second input from the output of the element 43 of the delay block 16 delay continues

to give a signal in the form of a logical O, prohibiting the operation of the N-8 circuit and, consequently, the P-6 circuit on the first input. Does not work, being in the initial 5 state, the trigger 47 of the delay block 16 and from its output Q through the element IL AND-E 48 to the fourth input of the circuit And 6 continues to receive a signal in the form of a logical O, which prohibits its operation by the rest

10 entrances.

The NE-40 element of the failure unit 13 is triggered and a signal is set at its output as a logical O, since its first input of the AND-NOT element 40 at this time interval is given a signal as logical 1 from the first output of the amplitude discriminator 4, and on the second - from the output of the Q trigger 37 (Fig. 4).

The failure signal (Fig. 5, graph 59), s

0, the second output of the control unit 12 at the output Q of the flip-flop 42 of the failure unit 13 is set as a logical 1, since the input j of the flip-flop 42 is outputted from the output of the AND-NOT element 40 as the logical O, and to the input K from the output the element 41 is a signal in the form of a logical g. Therefore, from the output Q of the flip-flop 42 of the failure unit 13, the inputs of the AND-NE element 44 and the driver 49 of the delay block 16 are given a signal

0 as logical 1, which does not prevent their operation (Fig. 4).

At time tg, the action of the control signal is terminated and at the fourth output of block 12 a signal is set to

5 as logical 1 (FIG. 4 and 5, plot 57), as a result, the output of the threshold level transmitter 10 returns to the initial, prior monitoring state, and the output of the element HE 39 of the fault unit 13 sets the signal as logical Oh, preventing the resetting of the trigger 42. including under the influence of random interference. Since the second input of the amplitude discriminator 4 again receives a signal from the initial, previous control level, and the first input does not change and the amplitude discriminator 4 is healthy, it turns off and its first output

0 sets the signal as logical O.

Therefore, according to the output signal (FIG. 5, plot 61), the trigger 47 of the delay unit 16 is set to the state where

5, its output Q is set as a logical 1, i.e. the signal of the initial, prior to monitoring, state, in view of which the AND signal of the NE-48 element at the fourth input of the AND 6 circuit continues to receive a signal in the form of a logical O, preventing the signals from passing through the rest of its inputs.

At time ti2, the prohibition signal in the form of a logical O stops (FIG. 5, plot 56). Under the influence of the signal from the first output of the amplitude discriminator 4 in the form of logical O, the delay element 43 of the delay block 16 stops the generation of the delay signal.

The end of control signal (FIG. 5, graph 63) from the third output of the control unit at the output Q of the flip-flop 33 of the memory block 9, at the output Q of the flip-flop 37 of the failure unit 13 is set a signal as logical O, and at the output of the Q flip-flop 37 - a form of logical 1. i.e. signals of the initial state, as well as after the influence of the installation signal O.

If the amplitude discriminator 4 is faulty, then in the time interval te-tg at the output of amplitude discriminator 4 the signal will not change and will remain as logical O. As a result, the output of the AND-HE40 element, as well as at the outputs of the AND-HE 38 and HE 39 elements set the signal as logical 1.

Therefore, the failure signal (Fig. 5, graph 59) at the output Q of the flip-flop 42 will set the signal as logical O. This signal is fed to the input of the AND-NOT element 44 and the driver 49 of the delay block 16 and prohibits their operation.

Thus, in the limiter, it is possible to increase the reliability of issuing a signal about exceeding the permissible vibration by preventing the issuance of a false signal by a faulty amplitude discriminator by delaying the issuance and performing a health check during a signal about dangerous vibration.

Claims (1)

Invention Formula The vibration limiter of a gas turbine engine containing a vibration sensor connected in series, a filter, an AC voltage to voltage converter constant and amplitude discriminator, tachometer signaling device, circuit I. OR-NOT circuit, NAND circuit, memory unit, threshold level adjuster, reference voltage sources, control unit, fault unit, external control trigger bus and installation bus connected to the first inputs of the memory block, the failure block and the And circuit; the second input of the latter is connected to the first output of the tachometer indicator, the second output of which is connected to the first input of the control unit, the second input of which is connected to the external control start bus, first The output of the amplitude discriminator is connected to the second inputs of the memory unit and the failure unit and the first input of the NAND circuit, the output of which is connected to the first input of the OR OR NOT circuit, the output of which is connected to the third input of the AND circuit, the output of the memory unit is connected to the second input the OR-NOT circuit and the first input of the threshold level setter, the second input of the latter is connected to the second output of the amplitude discriminator, and the third to the output of the reference voltage sources, the first output of the control unit is connected to the third inputs of the memory unit and the failure unit the fourth input of the latter is connected to the second output of the control unit, the third output of which is connected to the fifth input of the failure unit and the fourth input of the memory unit, and the fourth to the fourth input of the threshold level setter and the sixth input of the failure unit, so that in order to increase reliability, it additionally contains a delay unit, the first output of which is connected to the fourth input of the AND circuit, the second to the second input of the NAND circuit, and the third to the third input of the control unit, the first input of the delay unit is connected to the installed bus , the second to the fifth output of the control unit, the third to the output of the failure unit, the fourth to the first output of the amplitude discriminator, the fifth to the sixth output of the control unit, and the sixth to the seventh output of the control unit to the input of the memory block. Thrash mnos / goroshch batotyaf gtxoirg pshsai $ nous Ja la / edon04imen Yunppz tzhOarvs & uotrf oso # and / 0-gp zh-t no4 / 1, agodogo0оо1) / pyovrag y / aya / gxovff he fWMsnj} ywaugodufi zlDWtfg sho lsh & noi fiowisg UIQ / (/ 0a / 0 # il & yupr, lyohrShpimo j / eocfou / oenrDHim ovoheek / shayohash shr nxHtdsgot gi ozhd 2 GF C 81 61 ngooa