SU1537856A1 - Vibration of limiter for gas-turbine engine - Google Patents

Abstract

The invention makes it possible to increase the reliability of the vibration limiter of the CCD by preventing false alarms from exceeding the permissible vibration level. At the time of monitoring, control signals in the form of a sequence of pulses begin to flow to the inputs of the memory block 11, the AND 14 circuits of the setpoint adjuster 12 of the threshold level, and the failure block 10. From the output of the memory block 11, the signal corresponding to the output state of the amplitude discriminator 4 at the time the control starts through the input of circuit 15 OR NOT and circuit 6 And goes to the actuator 7, keeping the state of the latter unchanged during control if the limiter is healthy. When the control signal arrives, the failure unit 10 memorizes the state of the output of the amplitude discriminator 4 at the time the control starts, and then, in the process of control, analyzes the change of this state. The presence of feedback from the output of the amplitude discriminator 4 through the unit 12 of the threshold level to its second input provides a signal that the vibration is exceeded during fluctuations of the signal at its first input. In the absence of revolutions of a certain level or in the presence of a malfunction in the amplitude discriminator 4 circuits, the outputs of the tachometer alarm 5 and the failure unit 10, respectively, on the inputs of the circuit 6 receive signals in the form of a logical "O", prohibiting the generation of a signal that the permissible vibration level is exceeded. This embodiment of the device increases the reliability of its work. 5 il.

Description

(21) 4315506 / 25-06

(22) 10/12/87

(46) 01/23/90. Bul Number 3

(72) V.I. Mikhaylenko and G.A. Dushenko

(53) 621.438-55 (088.8)

(56) USSR Author's Certificate No. 502552, cl. F 02 C 9/00, 1973.

(54) LIMITER OF GAS TURBINE ENGINE VIBRATION

(57) The invention makes it possible to increase the reliability of the vibration limiter of the CCD by preventing false alarms from exceeding the permissible level of vibration. At the time of monitoring, control signals in the form of a sequence of pulses begin to arrive.

to the inputs of the memory block 11, the AND 14 scheme, the threshold level adjuster 12 and the failure unit 10. From the output of memory block 11, the signal corresponding to the output state of the amplitude discriminator 4, at the time of the start of monitoring, the input of the OR-NO 15 circuit and the AND 6 circuit goes to the actuator 7, saving the state of the last

Shit gtp chi signal

I-NOT N 11 OstoNaca- And 6 Nizm unchanged during the control, if the limiter is healthy. When the control signal arrives, the failure unit 10 memorizes the state of the output of the amplitude discriminator 4 at the time the control starts, and then, in the process of control, analyzes the change of this state. The presence of feedback from the output of the amplitude discriminator 4 through the unit 12 of the threshold level to its second input provides a signal that the vibration is exceeded during fluctuations of the signal at its first input. In the absence of revolutions of a certain level or in the presence of a fault in the circuits of amplitude discriminator 4, the outputs of the tachometric signaling device 5 and the failure unit 10, respectively, on the inputs of circuit 6, receive signals in the form of a logic O, prohibiting the generation of a signal that the permissible vibration level is exceeded. This embodiment of the device increases the reliability of its work. 5 il.

Analog cot cash

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The invention relates to the field of automatic control and monitoring of gas turbine engines (GTE), in particular, to devices for limiting vibrations.

The purpose of the invention is to increase the availability of the vibration limiter of a gas turbine engine by preventing a false signal of exceeding the permissible vibration level by providing for performance monitoring.

FIG. 1 shows the structural scheme of the vibration damper of the CCD; in fig. 2 is a block diagram of the threshold level setter; in fig. 3 is a block diagram of the control unit; in fig. 4 is a block diagram of the failure block and its connections; figure 5 - time diagram of the work is limited in the control of health.

The vibration limiter of a gas turbine engine (FIG. 1) contains a vibration sensor 1 connected in series, a filter 2, a converter 3 and an amplitude discriminator 4, a series-connected tachometer alarm 5, circuit AND 6 and an actuator 7, indicator 8, control unit 9, unit

10 failure, memory block 11, threshold level adjuster 12, sources 13 (reference voltage, AND-NO circuit 14

the OR-NOT 15 circuit, the external control start bus 16 and the installation bus 17 connected to the first inputs of the control unit 9, the failure unit 10 and the unit

11am and the second input of the circuit AND 6, the third input of which is connected to the input of the indicator 8 and the output of the failure unit 10, the second input of which is connected to the input of the indicator 8 and the output of the failure unit 10, the second input of which is connected to the first output of the amplitude discriminator 4, the second input the memory block 11 and the first input of the NAND 14 circuit, the second input of which is connected to the first output of the control unit 9, and the output to the first input of the OR-NOT circuit 15, the second input of which is connected to the first input of the threshold level setting unit 12 and the output of the block 11 memory, and the output - to four th input AND circuit 6, the bus 16 external trigger control is connected to the second input of the control unit 9, the third input of which is connected to the second output of the tacho signaling device 5, the second, third and fourth outputs

ABOUT

S

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five

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five

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respectively to the third, fourth and fifth inputs of the failure unit 10, and the fifth output to the second input of the threshold 12 threshold level, the third input of which is connected to the second output of the amplitude discriminator 4, the fourth input to the output of the sources 13 of the reference voltage, and the output is connected to the second input of the amplitude discriminator 4, the third and fourth outputs of the control unit 9 are connected to the third and fourth inputs of the memory unit 11.

The threshold level adjuster 12 contains keys 18, a key control circuit 19 and resistive dividers 20, and a control block 9 (FIG. 3) contains a reference frequency generator 21, a pulse counter 22, a trigger 23, a driver 24, an OR-NE 25 circuit, a decoder 26, OR scheme 27.

Failure unit 10 (FIG. 4) contains a HE 28 inverter, an OR element 29, a trigger 30, an AND-HE element 31, an AND-HE element 32, an HE inverter 33 and a trigger 34.

The limiter works as follows.

After supplying the supply voltage with the installation signal O (Fig. 5a), the control unit 9, as well as the memory unit 11 and the failure unit Yu, are reset, from the output of the control unit 9 (Fig. 5d) to the input of the I- circuit. NOT 14, from the output of the memory block 11 (FIG. 5k), the input of the OR-NO 15 circuit and the output of the failure unit 10 to the input of the AND 6 circuit (FIG. 3N) receive signals in the form of a logical 1, permitting the normal operation of these circuits. At the same time, the installation signal O (Figs. 1 and 5a), entering the input of circuit 6, prohibits its operation, thus preventing its possible operation and issuing a spurious signal at the moment the power is turned on.

The signal is in the form of alternating voltage, proportional to the vibration level of the GTE case and varying in both amplitude and frequency, from vibration sensor 1 through filter 2 of a controlled frequency range and through alternating voltage converter 3 to a constant input to the amplitude discriminator 4 and at the same time to the output of the device for recording the value of the transformed constant eg 15

20

51537856. 6

(analog signal, FIG. 1), on the reference frequency generator 21. For example, to the registrar. If there are moves of the decoder 26, the signals controlled by vibrations that do not exceed the permissible, or at the moment of control as the after-voltage level at the first input does not exceed the predetermined voltage level at the second input of the amplitude discriminator 4 and from its second output the signal for example, in the form of a logical O, it enters the inputs of the failure unit 10, the memory unit 11, and the NAND 14 circuit. From the output of the NAND 14 circuit, the inverted signal in the form of a logical 1 is fed to the input of the OR-NAND circuit 15, another input from which the power is turned on drove as a logical 1 from the output of block 11 of memory. Next, the signal from the output of the OR-NOT 15 circuit in the form of a logical O is fed to the input of the AND 6 circuit, the two remaining inputs of which receive signals from the output of the failure unit 10 and the tachometer signaling device 5.

The presence of a signal with a logic level from the control block 9 to whom O on any of the circuit inputs does NOT AND 14 prohibit the input, prohibits for time, and 6 does not trigger the actuator 7. When the revolutions increase to a certain level, the tachometer signaling device, the torus 5 and, from its output, the signal in the form of a logical 1 is fed to one of the inputs of the circuit 6, thereby allowing the rest of the signals through to the other inputs to pass through this circuit. As the speed increases from another output of the detector 5, the first input of the OR-NOT 25 circuit of the control unit sends a signal in the form of a logical O to the input of the imaging unit 24 of the control unit 9. A similar signal (Fig. 5b) External control start through another input of the OR-NO 25 circuit of the control unit 9 can be received at the input of the imaging unit 24, for example, from an operator or a specific device of the automated control system. At the moment the signal arrives in the form of a logical O, the input of the former 24 of the control unit 9 is triggered, and from its output a pulse in the form of a logical O arrives at the input of the trigger 23, as a result

the trigger 23 is switched from its high vibration level as well, when it enters the 22I of the 1I Control signal at one of the inputs of the counter, the signal in the pulse output receives a signal in the form of a loop J2 of the output threshold level

and it begins to read - the last signal is formed as

constant voltage (e.g.

The pulses (Figs. 5c, 3f) begin to flow to the inputs of the memory block 11, the AND-14 circuit, the threshold level adjuster 12, and the failure block 10 (Fig. 4).

The memory block 11, by the memory signal 1 And (Fig. 5b), memorizes the signal level, which is at the output of the amplitude discriminator 4 at the moment of the start of the control. From the output of the memory block 11, a signal corresponding to the output state of the amplitude discriminator 4 (for example, in the form of logic 1, if the vibrations are below the permissible level), through the input of the OR-NO 15 circuit and the AND 6 circuit enters the actuator 7, understanding of the latter, which existed before the beginning of the control.

The signal of the Interdiction Inductive Signal (Fig. 5d), by means of controlling the passage through it of signals from the output of amplitude discriminator 4 to the input of circuit 30 OR-NOT 15.

Therefore, the operation of the amplitude discriminator 4 in the process of performance monitoring does not change the state of the actuator 7.

The failure unit 10, upon receipt of the 1I Memorization signal (Fig. 5b), stores the output state of the amplitude discriminator 4, which exists at the time of the start of the control.

By means of the 1I Control signal (Fig. 5e) for the duration of this signal, the level of the output signal 45 of the setting device 12 of the threshold level, depending on the level of the signal from the output of the memory block 11, is changed so that the amplitude discriminator 4 is triggered if the latter is healthy.

So, for example, if the amplitude discriminator 4 is healthy and before the start of the performance test, it issued a signal that the tolerance is exceeded35

40

50

geological 1

impulses coming from the output

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generator 21 reference frequency. From the outputs of the decoder 26, the control signals (at the time of control) in the form of post-

The pulses (Figs. 5c, 3f) begin to flow to the inputs of the memory block 11, the AND-14 circuit, the threshold level adjuster 12, and the failure block 10 (Fig. 4).

The memory block 11, by the memory signal 1 And (Fig. 5b), memorizes the signal level, which is at the output of the amplitude discriminator 4 at the moment of the start of the control. From the output of the memory block 11, a signal corresponding to the output state of the amplitude discriminator 4 (for example, in the form of logic 1, if the vibrations are below the permissible level), through the input of the OR-NO 15 circuit and the AND 6 circuit enters the actuator 7, understanding of the latter, which existed before the beginning of the control.

The Signal OI of the Prohibition (Fig. 5d), which comes from the control block 9 to the input of the NAND 14 circuit, prohibits for

m conducting control of the passage through it of signals from the output of the amplitude discriminator 4 to the input of the circuit OR NOT 15.

Therefore, the operation of the amplitude discriminator 4 in the process of performance monitoring does not change the state of the actuator 7.

The failure unit 10, upon receipt of the 1I Memorization signal (Fig. 5b), stores the output state of the amplitude discriminator 4, which exists at the time of the start of the control.

By means of the 1I Control signal (Fig. 5e) for the duration of this signal, the output level of the setpoint 12 threshold level, depending on the signal level from the output of the memory block 11, is changed so that the amplitude discriminator 4 is triggered if the latter is in good condition.

So, for example, if the amplitude discriminator 4 is healthy and before the start of the performance test, it issued a signal of exceeding permissible

After the end of the performance test, the output of the decoder 26, via the OR circuit 27, a signal arrives at the input of the trigger 23 of the control unit 9, which sets the trigger 23 to its initial state. From the output of the latter to the counter input 22 pulses, a signal prohibits the functioning of 15378568.

7B), which exceeds the voltage (for example, 10%) from the output of the inverter 3 of the alternating voltage to the amplitude discriminator 4 constant at the first input in case of maximum permissible vibration, and ensures that the amplitude discriminator 4 turns off and returns its output signal to the level, the 10th implementation of the counter 22 pulses. when the signal of exceeding the permissible Simultaneously at the time of termination

control unit from control unit 9 to memory unit 11, failure unit 10 is given an IO End of Control signal

Before the start of monitoring the operability, 15 (Fig. 5e) is set to the initial state of the signal that the state of the vibration is exceeded, and to the AND 14 scheme (Fig. 5d), the resolution is in the form of a logical 1 for the normal passage of signals from the amplitude discriminator through it - it forms a signal in the form of a constant Q min. ° 4.

voltage (for example, -0.1 V), if the vibration level exceeds that, and in the absence of vibration, the amplitude discriminator 4 triggers, and the last

no vibration is given.

And vice versa, for example, if the amplitude discriminator 4 is healthy and

did not give out, then when the 1I Control signal arrives at the setpoint 12 threshold level output, the output is valid, then the voltage level at the first input of the amplitude discriminator 4 exceeds the preset value

The operating time of the signal 1I. The control of the 55th voltage level on its second one generates a signal that the vibration is exceeded. the input and amplitude discriminator 4 By means of the 1I Failure signal is triggered and, from its output, the signal about (FIG. 5a) the failure unit 10 generates a failure signal (malfunction) to amplify the excess vibrations of the permissible level1

n in the form of a logical 1

of the discriminator 4 in the form of logs-39 to the inputs of memory block 11, block 10

failure and through the circuits 8 and AND-NOT 14 and OR-NOT 15 to one of the inputs of the circuit AND 6.

In other words, if the output signal of the latter during the operation of the 1I Control signal has not been reversed compared to its output signal before starting the health check.

In this case, the failure signal (malfunction) with the logic level from the output of the failure unit 10, entering the input of circuit 6, prohibits the passage through it of other signals arriving at its other inputs, i.e. by performing a health check, a false signal from the faulty device is prevented.

At the same time, the same signal of failure, entering the input of the indicator 8, triggers the latter, signaling a malfunction of the device.

If the amplitude discriminator 4 is healthy, then at the output of the failure unit 10, the signal in the form of the 1and Failure signal is generated in the form of a logical 1, i.e. output level

The failure unit 10 remains unchanged, and entering the input of the AND 6 circuit does not prevent the passage of other signals through its other inputs.

After the end of the performance test, the output of the decoder 26, via the OR circuit 27, a signal arrives at the input of the trigger 23 of the control unit 9, which sets the trigger 23 to its initial state. From the output of the latter to the input of the counter 22 pulses, a signal prohibits the operation of the counter 22 pulses. Simultaneously at the time of termination

 If the vibration level exceeds

permissible, the voltage level at the first input of the amplitude discriminator 4 exceeds the pre-set

voltage level at its second input and amplitude discriminator 4 is triggered, and from its output a signal about

exceeding the vibration tolerance level1

n in the form of a logical 1

9 to the inputs of the memory block 11, block 10

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failure and through the circuits 8 and AND-NOT 14 and OR-NOT 15 to one of the inputs of the circuit AND 6.

The output signals of the memory block 11 and the failure block 10 do not change their state, since the blocks operate only during the performance monitoring process.

If all the inputs of the circuit 6 have signals with a logic level of 1, then the circuit 6 operates and actuates the actuator 7.

The timing diagram of the operation of the vibration limiter of GTZ in the process of performance monitoring is graphically represented in FIG. five.

The signal 1and the memory at the output of the memory block 11 establishes a signal with a logic level 1 (Fig. 5k), if during the time period t, -tJ, the logic output O was set at the second output of the amplitude discriminator 4 (Fig.5i). From the output of the memory block 11, a signal with a logic level 1 is applied to the input of the OR-NO 15 circuit (FIG. 4) and to one of the inputs of the key control circuit 19 of the sensor 12 of the threshold level (FIG. 2).

The receipt of the 1I Memorizing signal to the input T of the trigger 30 of the failure unit 10 (Fig. 4) in this case does not cause the trigger 30 to switch (since the input I of the trigger 30 30 directly from the output of the amplitude discriminator 4 receives a signal with a logic level O, and the input K the trigger 30 is a signal inverted by the inverter NOT 28 of the failure unit 10 with a logic level 1, i.e. the trigger 30 remains in the initial state, and therefore from the output Q of the trigger 30 the signal with the logic level O is fed to the second input of the AND circuit -NOT 31, ac output Q trigger 30 signal level logical 1 - to the input circuit AND-NOT 32 of the block 10 failure (Fig. 4).

The interdiction signal OI with a logic level of O acts for a period of time (Fig. 5d) and is fed to the input of the AND-HE circuit 14, prohibiting the monitoring time for passing through its first input of signals from the output of the amplitude discriminator 4 to the input of the OR-HE circuit 15 (Fig. 1 and 4) during the production of a health check. Therefore, if there is an OI ZARPET signal, the input of the OR-NOT 15 circuit during t2-tt is a signal with a logic level of 1, which does not interfere with the OR-NOT 15 circuit. Since the output of memory block 11 to the input the OR-NOT 15 circuit in this case is given a signal with a logic level of 1, then a signal with a logic level of O will continue to be output from the last output to the circuit input AND 6

The signal 1I Control (Fig.5e

The input to the key control unit 19 of the setpoint 12 knob of the threshold level (Fig. 2), if there is a signal at its first input with a logic level 1 from the output of the memory block 11, the key control circuit 19 is triggered by means of the keys 18 and the resistive dividers 20 ( Fig. 2) forms, at the output of the quad sensor 12, a threshold

go level output low

50

level (for example, Зг 0,1В, the level of which provides the triggering of the amplitude discriminator 4 at low levels of vibrations, including on an idle product. 55

As a result, the amplitude discriminator 4, if it is in good condition, is triggered over time tr-t $

. jr 20

25 30 .Q

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(Fig. 5i). When the amplitude discriminator 4 is triggered, its first output to one of the inputs of the unit 12 of the threshold level receives a signal that lowers the reference voltage to the second input of the amplitude discriminator 4 to a predetermined value, thereby ensuring that a signal is output that the permissible level is exceeded. vibrations with a possible decrease in the voltage value at its first input due to fluctuations in the level of vibrations within predetermined limits. The signal from the second output of the discriminator 4 with a logic level 1 (Fig. 5i) is fed to the input of the circuit AND-HE 14, the input of memory block 11 and the inputs of the inverter HE 28, the input I of the trigger 30 and the input of the element AND-HE 32 of the failure unit 10 (figure 4).

The AND-NE 14 circuit does not work and the signal level at its output does not change, since at this time the IOA Ban signal with a logic level O (Fig. 5d, and) is fed to its input. The output signal of memory block 11 remains the same since the signal 1I Memorization at time tt 2 is absent. Therefore, at time t s tt s, the AND-HE element 32 of the failure unit 10 is triggered, since both its inputs are at this time supplied with a logic level to one input - from the output of amplitude discriminator 4, and to the other - from the output Q of the trigger 30 failure block 10 (FIG. 4). As a result, at the common point of connection of the outputs of the AND-FiE elements 31 and 32, a signal with a logic level O is set at input I of trigger 34 and input of inverter 33, and a signal with logic level 1 at input K of trigger 34 (Fig. 4).

In the period of time t 3 t, the signal 1and Failure arrives at the input T of the trigger 34 (Fig. 5g). The trigger 34 does not switch and remains in the initial state, i.e. at the output Q of the trigger 34, connected to the input of the circuit AND 6 and the indicator 8, there remains a signal with a logic level of 1, which does not interfere with the operation of the circuit AND 6.

If the amplitude discriminator 4 is faulty, then when it feeds into its second input, for example, U3T -0.1V, it does not work and the signal at its second output remains the same, with a logic level of O. This signal arrives at the input of the I- element. NOT 32, does not cause it to trigger at a time. Therefore, the outputs of the elements AND-NOT 31 and 32, the input I of the trigger 34 and the input of the inverter HE 33 sets the signal with a logic level 1, and the input K of the trigger 34 of the failure unit 10 - a signal with a logic level O In this connection 1I Failure to the T input of the trigger 34 triggers the trigger 34 and at its output Q after the termination of the 1I Failure signal, a potential is set with a logic level of O. This signal goes to one of the inputs of the circuit 6 and the output of the indicator 8.

At time t, the action of the 1I Control signal (Fig. 5e) ceases and the output of the threshold level adjuster 12 is set to the previous, prior to the control level. As a result, the amplitude discriminator 4 switches if it is healthy, and its output is set to the previous, previous control, level logical O (Fig.5i).

At time t, the action of the interdiction signal OI with a logic level O is terminated and a signal with a logic level 1 which does not interfere with the operation of AND-circuit 14 (fig.5d) is input to the input of the circuit IS-HE 14 from the control unit 9.

In the time interval, the input of the memory block 11 and the OR element 29 are sent to the R input of the trigger 30 and the End of Control OI signal (Fig. 5h) is sent, which sets them to their initial state. At the same time, the output of memory block 11 to the second input of the OR-NOT 15 circuit is signaled with a logic level of 1, which does not interfere with the operation of the OR-NOT 15 circuit.

Verification of the amplitude discriminator 4 is over, the vibration limiter is ready for normal operation.

The arrival of a signal with a logic level O at one of the inputs of the AND 6 circuit (Figs. 1 and 4) prohibits the passage of the remaining signals arriving at its other inputs, and blocks the activation of the actuator 7 until the next monitoring cycle if the amplitude discriminator 4 malfunctions is eliminated in the process work. Signal flow with log level

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A cc b to the input of indicator 8 includes the last one, which signals the presence of a malfunction (failure) of an inoperable amplitude discriminator 4.

Thus, during the health check of the amplitude discriminator 4 when IV (x 0 and in the presence of the latter’s failure, block 10 fails to provide an indication to the indicator 8 of the fault amplitude discriminator 4 and blocks the activation of the actuator 7.

During the period of time tfe-t7, the input of the memory block 11 and the OR element 29 are sent to the R input of the trigger 30 (Fig. 4) and the End of Control OI signal is sent (Fig. 5h), which sets them to the initial state.

If the second output of the amplitude discriminator 4 is set to logic level 1, which corresponds to the state of issuing a signal that the permissible vibration level was exceeded (Fig. 5l), then after applying the 1I Memory signal (Fig. 5c) to the inputs of memory 11 and The failure unit 10 (FIG. 4) at the output of the memory unit 11 is set to a signal with a logic level O (FIG. 5m), and the trigger 30 of the failure unit 10 is set to a state at which its output Q will receive a signal with a logic level 1 , and output Q - a signal with a level of logical th O.

From the output of memory block 11, a signal with a logic level of O is applied to the input of the OR-NOT 15 circuit (FIGS. 1 and 4) and to the input of the key management circuit 19 (FIG. 2) for the entire duration of the health check (FIG. 5m). The arrival at the second input of the OR-NOT 15 signal with a logic level O keeps at its output a logic level 1 for the entire time the health check is performed, which ensures that the state of the actuator 7 remains unchanged if it was turned on before the control began.

The Signal OI Ban (Fig. 5d), entering the input of the AND-NO circuit 14 (Fig. 4), for the entire monitoring cycle prevents the passage) through its other input the signal changing from the output of the amplitude discriminator 4, if the latter is intact, and therefore

13

changes in the output signal levels of the amplitude discriminator 4 from 1 to 0, (or from 0 | to 1), as in the previous case, as well as after termination of the 1I Control signal, during the health check in the time interval (or) are not transmitted to the actuator 7

At time t, when the key control unit 19 of the setting unit 12 of the threshold level (FIG. 2) of the control signal 1I (FIG. Ze) arrives at the first input and if there is a signal at the second input from the output of the memory block 11 with a logic level O (FIG 5m) the latter operates and, using keys 18 and resistive dividers 20, generates a signal at the output of resistive dividers 20, for example, U} T 7.0 V, which is fed to the second input of amplitude discriminator 4.

The L 3r 7B level ensures that the amplitude discriminator 4 is turned off even when the level of the signal at its first input corresponds to the maximum permissible vibrations, for example, iprm 5p in

Amplitude discriminator 4 if

it is healthy, at the time t% it switches and a signal with a logic level O is established at its second output (Fig. 5l). This signal is applied to the corresponding inputs of the NAND circuit 14, the memory block 11 and the failure block 10 (Fig. 4).

The AND 14 scheme does not trigger during the time interval tj-tj-, since during this time the IOI Ban signal (Fig. 3g) continues to arrive at its input with a logic level of O. The output signal from the memory block 11 during the time interval tj -t $ also does not change. The NAND element 32 of the failure unit 10 does not operate, since its input from the output Q of the trigger 30 is given a signal with the level of the logical O.

In the time interval, only the AND-HF 31 element of the failure unit 10 is triggered (during this period signals are output to its outputs with a logical loss of 1 from the output Q of the trigger 30 and from the output of the HE 28 inverter, Fig. 4) and a signal is generated at its output level logical o.

avi153785614

In time tj-t on

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the input T of the trigger 34 of the block 10 failure (figure 4) receives the signal 1I Failure (fig.5zh). Due to the fact that in the time interval of Lg-C5 a signal with a logic level O is supplied to the 3-input of the trigger 34 and to the input K - a signal with a logic level 1 from the output of the inverter 33 NOT, after the influence of the 1I Failure signal, the trigger 34 is set to at which the Q output is set to a signal with a logic level of 1, that is, the level corresponding to the initial state, as well as after the OI signal of Setup O. its normal functioning.

At time t5, the action of the control signal 1I is stopped (Fig. 5e), the key management circuit 19 is turned off, the switches 18 and the keys 18, the signal level at the output of the threshold level generator 12 returns to the initial, previous control state. As a result, the amplitude discriminator 4 is triggered (FIG. 5 l) and at its output a signal is set with a logic level, i.e. the same as before npoBtp-koi health.

At the moment of time t4, the action of the IOA Ban signal (fig.5g) stops and the signal from the output of the amplitude discriminator 4 through the input of the AND-NO circuit 14 starts to be input to the input of the OR-NO 15 circuit (FIG. 4), the signal still present on the other input with a logic level O from the output of the memory block 11 (Fig. 5m).

At the time interval tfe-t7, from the output of control block 9, the terminator OUT signal (FIG. 5z) arrives at the input R of trigger 30 of failure block 10 (Fig. 4), and the trigger 30 is reset to its initial state. OI Signal Settings The health check cycle is terminated at the input of the AND-HI circuit 14 from the output of control block 9, to the input of the OR-NE circuit 15 from the output of memory block 11, to one of the inputs of the AND 6 circuit from the output of fault block 10, as well as after turning on the power , signals with a logic level of 20

1, and the vibration limiter is ready for operation.

Thus, the vibration limiter checks the operability of the amplitude discriminator 4, which is in the state of giving out a signal of excessive vibration, and, despite the switching of the amplitude discriminator 4, during monitoring ensures that the actuator 7 is switched on while the amplitude scanner is working 4. If the amplitude discriminator 4 is faulty (or a signal is supplied to its first input, for example, with the voltage Ugx 7, the output voltage OBc of the inverter 3 of an alternating voltage to constant , which corresponds to the fault of the latter), then in the time interval s the discriminator 4 does not switch and at its second output the signal with a logic level 1 remains unchanged. The output CHI levels of the AND 14 scheme and the memory block 11 (25 m) of Fig. 5 m do not change for the reasons described above, and the signal level at the output Q of the flip-flop 34 of the failure block 10 changes.

In the time interval, a signal with a logic level of O is supplied to the input of the NAND element 31 from the output of the inverter 28; therefore, a signal with a level of 1 is set at its output. A signal with a level of 1 logical is also set at the output of the NAND 32 element, because since the start of control from the output Q of the trigger 30 (described above), a signal with a logic level O is applied to its input.

Consequently, in the time interval t -t 5 with a common point of output of the AND-NE elements 31 and 32, input 3 of trigger 34 is given a signal with a logic level, and input K of a trigger 34 through an HE inverter 33 — with a logic level of O. Therefore, The T-input of the trigger 34 in the time interval the 1I Failure signal (Fig. 5g) causes the switching of the IK-trigger 34 and from the time t on the output O of the latter a signal is set with a logic level

thirty

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the amplitude discriminator 4 that malfunctions (malfunction) 4. By stopping the signal passing through the signal circuit 6 with a logic level 1 when the amplitude discriminator 4 fails, the actuator 7 is turned off, i.e. By monitoring the operability, false alarms are prevented when the amplitude discriminator 4 is actively failing, thereby increasing the reliability of the device, ease of operation and reliability of the signals generated by this device.

Thus, the limiter provides detection of the failure of the vibration level control channel both on an inoperative gas turbine engine, which allows monitoring and checking the device’s performance without removing the latter from the object and thereby reduces the pre-launch preparation time of the gas turbine engine and the engine. TBG without changing the state of the actuator. This increases the reliability of the signal about the excess of dangerous vibration and allows the device to be used in the systems of automated control of the object, ensuring prompt measures for the timely elimination of malfunctions that could lead to emergency situations.

Claims (1)

Invention Formula 40 The vibration limiter of a gas turbine engine containing a vibration sensor connected in series, a filter, a converter and an amplitude discriminator, a tachometer warning lamp connected in series, an AND circuit and an actuator, an indicator that, in order to improve reliability, it additionally contains control unit, failure unit, memory unit, setting unit threshold: about level, reference voltage source, NAND circuit, OR – N circuit, external control start bus and installation bus, sub50 A. This signal stops passing to the first inputs of the control unit, the failure unit and the memory unit and the second input of the AND circuit, the third input of which is connected to the input of the indicator On the other inputs of the circuit And 6, and causes the operation of the indicator 8, the signal 0 five 0 five the amplitude discriminator 4 that malfunctions (malfunction) 4. By stopping the signal passing through the signal circuit 6 with a logic level 1 when the amplitude discriminator 4 fails, the actuator 7 is turned off, i.e. By monitoring the operability, false alarms are prevented when the amplitude discriminator 4 is actively failing, thereby increasing the reliability of the device, ease of operation and reliability of the signals generated by this device. Thus, the limiter provides detection of the failure of the vibration level control channel both on an inoperative gas turbine engine, which allows monitoring and checking the device’s performance without removing the latter from the object and thereby reduces the pre-launch preparation time of the gas turbine engine and the engine. TBG without changing the state of the actuator. This increases the reliability of the signal about the excess of dangerous vibration and allows the device to be used in the systems of automated control of the object, ensuring prompt measures for the timely elimination of malfunctions that could lead to emergency situations. Invention Formula The vibration limiter of a gas turbine engine containing a vibration sensor connected in series, a filter, a converter and an amplitude discriminator, a series tachometer warning device, an AND circuit and an actuator, an indicator different in that it also contains a control unit , failure block, memory block, threshold set point: about level, reference voltage source, AND – NOT circuit, OR – NO circuit, external control start-up bus and installation bus, under connected to the first inputs of the control unit, the failure unit and the memory unit and the second input of the AND circuit, the third input of which is connected to the indicator input 17 and the output of the failure unit, the second input of which is connected to the first output of the amplitude discriminator, the second input of the memory unit and the first input of the NAND circuit, the second input of which is connected to the first output of the control unit, and the output to the first input of the OR NOT circuit, the second the input of which is connected to the first input of the threshold level setter and the output of the memory unit, and the output to the fourth input of the I circuit, the external control start bus is connected to the second input of the control unit, the third input of which is connected to the second output of the tachometer 3785618 the second, third, and fourth outputs, respectively, to the third, fourth, and fifth inputs of the failure unit, and the fifth output, to the second input of the threshold level setter, the third input of which is connected to the second output of the amplitude discriminator, the fourth input to the output sources the reference voltage, and the output to the second input of the amplitude discriminator, the third and fourth outputs of the control unit are connected to the third and fourth, inputs of the memory unit. ten Analog signal