SU1696870A1 - Data recorder - Google Patents

Abstract

The invention relates to a measuring technique and can be used to create instruments with a light scale, in systems for recording information on a photosensitive medium, as well as in instruments with mechanical indicator and recording devices. The invention allows to simplify the device by changing the algorithm for processing the input information by increasing the information load on the code conversion units. The device contains three code conversion units, a registration unit, and a generator. Due to the appropriately selected generator frequency, the input data recording is the formation of a series of illuminating lines on an LED array, which is used to illuminate the photosensitive medium. In the latter, the sampling information is presented in the form of a histogram of the upper and lower bits of the input number. 3 Table 2 Il.

Description

The invention relates to a measuring technique, can be used to create instruments with a light scale in information recording systems on a photosensitive medium, as well as in instruments with mechanical indicator and recording devices.

The purpose of the invention is to simplify the device.

FIG. 1 shows a functional diagram of the device; in fig. 2 shows an example implementation of unit 1 of the device.

The device contains the first, second and third blocks 1-3 conversion codes, bgok 4 registration, the generator 5 pulses.

Block 1 contains the converter 6 codes and the element OR 7.

The device works as follows.

The input of the device receives a code of the number in the form NM mN + M. The inputs of block 1 receive the code of the lower bit M, and the inputs of blocks 2 and 3 receive the code of the high bit N. The device operates in two cycles. Tact A corresponds to the presence of the potential of a logical unit at the direct output of generator 5, and cycle B corresponds to the potential of a logical zero. In such a dA, block 1 converts the code of the number M into an m-bit code combination of the form 11.,. 1, where m is the number of inputs of the least significant bits in block 4. The outputs of block 2 are in the third state. Block 3 transforms the code of the number N into an n-bit code combination of the form 00 ... 011 ... 1, containing

N units. Consequently, in time A, an m-bit code of the type 11 ... 1 and an n-bit code of the type 00 ... 011 ... 1 containing N units arrive at the inputs of block 4 according to the least significant bits.

ABOUT

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00 h | ABOUT

- on senior razh dam. In cycle B, block 1 converts the code of the number M into a t-bit code combination of the form 00 ... 011 ... 1 containing M + 1 units. Block 2 transforms the code of the number N into a bit code combination of the form 00 ... 010 ... O, containing a unit at the N-t 1st position. The outputs of block 3 are in the third state. Consequently, in time B, an nn-bit code of the type 00 ... 011 ... 1 containing M + 1 units is supplied to the inputs of block 4, the least significant bit, and the most significant bit of an n-bit code of the type 00 .. .010 ... O, containing a unit on the N + 1st position. As a result, N full upper bits of block 4 of mN elements are excited in tact A, and in cycle B - N + 1 st partial higher bit of M + 1 elements. The frequency of the clock generator is chosen so that the information receiver perceives the output The signal is in the form of a continuous contrast line from mN + M + 1 excited elements, which corresponds to the derivation of a number of the form mN + M.

The device is implemented using the KP580 series microcircuit as the basic element base and is designed to work with the information recorder on a film made on the basis of 224 LED elements (see Multiple monolithic linear scales for recording information on a photo film S. Abramov, PS Garba w et al., Electronic Engineering, Series 2, Semiconductor devices, 1980, issue 8 (143), pp. 54-58). The elements were included in matrix 72 (32.

An example of a specific job, usd.troyg, is when you enter the number 157 (224 values from 000 to 223 are recorded per film). At the input of the device in six cycles comes a series-parallel code number. input code is described in Table 1.

Vrezd conversion of a series-parallelel code into parallel 30 µs. The device works with two cycles. The clock frequency is 0.5 kHz. Tact A corresponds to the presence of the potential of a logical unit at the direct output of generator 5, and to cycle B, the presence of the potential of a logical zero. The operation of the device is described by the potential map given in Tables 2, 3. They use the following designations: B4 (C) - inputs of the higher bits of the 4 B4 block (m) - inputs of the lower bits of the 4 B1 block 1 of the B2 code conversion block 2 code conversions BZ - block 3 code conversions X - the third state of the outputs 8 clock cycle A four full high-order bits from 128 LEDs are energized, and to the beat B - the fifth incomplete high-order bit from 30 LEDs. With a clock frequency of 500 Hz, lines of 158 illuminated elementary sections are recorded on the moving film, which corresponds to the conclusion of the number 157 (when leaving zero, one elementary segment is illuminated). When the input signal changes, the recorded line has a certain length at each moment of time, as a result of which a histogram is built on the film reflecting the change in the input signal over time

Claims (1)

Apparatus for registering information comprising three code conversion units, a registration unit and a pulse generator, the information inputs of the first code conversion unit are information inputs of the lower order unit of the device, the information inputs of the second and third code conversion blocks are information inputs of the higher bits device, the direct output of the pulse generator is connected to the upstream input of the first code conversion unit, the outputs of which are connected to the information the inputs of the lower bits of the registration block, which is different in that. In order to simplify it, the outputs of the second and third code conversion blocks are connected to the information inputs of the higher bits of the registration block, the control inputs of the second and third code conversion blocks are connected to the inverse and direct outputs of the pulse generator, respectively. Table 1 Input device code to display information. Table2 Input code combinations of elements and blocks of the claimed device. Output code combinations of blocks of the claimed device. Table3 2 one srigL one FIG. l