SU1695290A1 - Data sorting device - Google Patents

Abstract

The invention relates to computing and can be used in information processing systems. The purpose of the invention is to increase speed. The device contains switch 1, memory block 4, data code converters 2 and 6, registers 3 and 7, controllable encoders 5 and 8. A random list is entered in the device. A sign of being in the list is stored in the code byte at the address corresponding to the least significant code. data, and the byte itself is stored at the address corresponding to the highest bit of the data code. In addition, the sign of the byte containing the sign of being in the list is stored by the most significant bits of the data code. Then bytes are selected that contain the signs of being in the list and, according to their values, the priority polling of the bits of these bytes. Managed encoders allow the issuance of an ordered list in either ascending or descending order 5 or more.

Description

The invention relates to computing and automation and can be used in information processing systems when implementing technical means of digital computers and discrete automation.

The purpose of the invention is to increase the speed of the device.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - | functional data code converter circuit; in fig. 3 - functional scheme of the controlled encoder; in fig. 4 and 5 are time diagrams of the device operation in input mode and output mode, respectively.

The device contains (Fig. 1) switch 1, data code converter 2, register 3, memory block A, controlled encoder 5, data code converter 6, register 7, controlled encoder 8, turns 9-13, information outputs 14 and 15, the output 16 of the input end and the input 17 of the installation.

Input 9 receives a signal to set the sorting mode in descending order, and input 10 receives a signal to assign a list to be received. The inputs 11 and 12 receive the sync signals T1 and T2, respectively. The input data code for list 13 is D. The outputs 14 and 15 receive, respectively, the lower (OML) and higher (OST) data codes of the ordered list, the output 16 is the output end signal, and the input 17 is the initial setting signal

Transducers 2 and 6 of data codes contain (Fig. 2) a decoder 18, groups of elements OR 19 and And 20 and a switch 21. Managed encoders 5 and 8 contain (Fig. 3) switch 22, a priority encoder 23 and a group of adders 24 modulo two.

FIG. 4 denote: a, b - sync pulses T1 and T2, respectively;

c, d are the high and low bits of the data code entering the device, respectively;

d, e — first and second bits of register 7;

W and — respectively, the first, second, and last bits of the output of memory block 4;

km - the first, second and last outputs of the converter 2;

nn - the first, second and last bits of register 3;

In FIG. 5, are indicated;

a, b - T1 and T2 clock pulses:

- in - a signal of reception of the list on an entrance 10;

d, d - first and second bits of register 7; e is the information output of the encoder 8; W - output end of the operation of the encoder 8; h, and the first and second outputs of the Converter 6;

 Km - outputs of memory block 4;

n - information output encoder 5;

about - output end of the operation of the encoder 5;

0 ps - transducer 2 outputs; tf - outputs of register 3. The proposed device is intended to organize the list of up to 27 data of 7 bits. As

5 senior 4 grade. Memory block 4 is an 8 x 16 matrix implemented on the basis of the K531RU8. The first converter 2 is designed as a three-bit binary to

0 eight-bit position code, first encoder 5 - as a converter of eight-bit position into a three-digit binary code, second converter 6 and encoder 8 - respectively

5 as converters 4-16 and 16-4. The device is implemented on the basis of the K555 series, in particular, switches 1.21 - on K555KP11, registers 3, 7 - on K555TM8, decoder 18 - on K555ID7, encoder 23 - on K555IV1,

0 adders 24 - to K555LP5.

The device works as follows.

The list entry mode is set by setting a single signal at input 10 and by setting the clock signals T1 (FIG. 4a) and T2 (FIG. 46). In the intervals between the signals T2 and T1, data codes (Fig. 4, c, d) are received at input 13, which switch 1 connects to its output.

0 In converter 6, the decoder 18 converts the value of the higher bits of the data into a unitary code that the OR 19 elements add to the previous state of register 7, and this new value through the switch 21 is fed to the information inputs of the register 7, where it is written on the falling edge of J2 ( Fig. 4, d, e). At the same time, at one of its second control input, the encoder 5 supports 1 at its output of the end of work connected to the enable input of the register entry 7. Thus, register 7 specifies the signs of being in the list corresponding to the highest bits of the incoming

5 data codes.

From block 4, by the state of the most significant bits of the data, the corresponding feature byte is selected (Fig. 4 g) and, in converter 2, this byte is added by OR with the unitary code generated by the decoder 18 of converter 2 from the lower bits of the data code (FIG. 4 , to m) and through the switch 21 is transmitted to the information input of the register 3, where it is entered along the leading edge T1 (Fig. 4, nn). Then the newly formed feature byte of T2 is stored in memory block 4. Thus, in the information bytes of block 4 of the memory, signs of being in the list are placed in accordance with the values of the lower bits of the data of the ordered list, and these bytes themselves are addressed in accordance with the values of the higher data bits of the ordered list.

The issuance of the ordered list is set by resetting the PR signal to O (FIG. 5, c). In this case, the information output of the cipher 5, which was in the unit value of the PR signal in the state of all units, goes to the state corresponding to the output state of block 4 (Fig. 5, n). If at the output of block 4 there is at least one indication of the presence in the list, the output of the end of operation of the encoder 5 is reset (Fig. 5, o) and writing to register 7 is prohibited.

Sorting the list in ascending order is determined by the level O at input 9. According to it in controlled encoders 5 and 8, switch 22 transfers the input code to the information inputs of the priority encoder 23, which at its information outputs generates a code corresponding to the attribute to which the highest priority is assigned. The adders 24, if O are present, at their first inputs transmit this code to the information output of the controlled encoder. Sorting in descending order is set by setting 1 at input 9. According to it, switch 22 transmits the low-order bit at its input to the high-order bit of its output, and vice versa. For example, the code 10000011 at the input of the switch 22 is transmitted to the input of the encoder 23 as code 11000001. Thus, the feature with the lowest priority is assigned the highest priority. At level 1 at their first inputs, adders 24 invert the code generated by the encoder 23. Thus, when the priorities of attributes change, the codes assigned to these features are preserved. FIG. 5 shows ascending sorting.

At the information output of the encoder 8 there is a code corresponding to that of the signs stored in register 7. which is assigned the highest priority. For example, level 1, in the first discharge of de register 7 (Fig. 5, d), corresponds to code 0000 (Fig. 5, e). This code, the switch 1 transmits to the input of the decoder 18 of the converter 6, as a result of which the corresponding element AND 20 blocks the transmission of the characteristic to the output of the switch 21 (FIG. 5, h).

Based on the information output of the encoder 8, a byte of features is selected from memory block 4 (FIG. 5, km), which, depending on the state of the encoder 5, which switch 1 transmits to the input of converter 2, is modified by the same in a way.

On the leading edge of T1 (Fig. 5, a), the modified byte of signs of the least significant bits is entered into register 3 (Fig. 5, tf). In addition, according to T1 with information

5 outputs of the device accept the code of the sorted data: from the output 14 - the younger bits, from the output 15 - the senior bits. According to T2 (Fig. 5, b), the feature byte of block 4 is modified.

0 After all the signs at the output of block 4 are discarded, a single code is set at the information output of the encoder 5, and a level 1 is set at the output of the request. It allows5 to write the modified byte of the high-order signs to register 7 by the falling edge T2 The code at the output of the encoder 8 is changed. For example, after resetting the feature in the first register deregister 7 to 1 in its second discharge (Fig. 5e), the encoder 8 generates the code 0001. In it, from block 4, the next feature byte is selected, and the process of issuing the sorted list continues.

5 After block 4 is selected, the byte corresponding to the last of G in register 7, and all its bits will be zeroed, on the falling edge 12 the last of 1 register 7 is reset. The information output of the encoder 8 is set to state 1111. At the output of the end of operation of the encoder 8, 1 is set (Fig. 5, g), which is transmitted to output 16 as the output end signal. Issuing signals

5 T1 and T2 terminate. All bits of registers 3 and 7 and cells of block 4 are zero, and the device is ready to receive the next list.

When powering up the memory cell

0 are set arbitrarily. For their initial zeroing, a preliminary extraction operation is performed, for which input 17 is given a signal of the initial setup of register 7 in the unit state. Then

5 at the inlet THAT is set to O, and T1 begins to arrive at the inputs 11 and 12. In the pro- cessing process, the bytes of all block 4 bytes are alternately sampled and reset. The end of zeroing is determined by the KB signal at output 16.

Thus, the incoming random list of data is memorized by their code values and the normalized list is issued in order of decreasing or increasing. The additional memorization of the attributes of bytes containing the attribute of being in the list allows excluding the idle polling of memory from the process of issuing and thereby significantly reducing the sorting process.

Claims (1)

The device for data sorting contains a switch, the first data code converter, the first register, the memory block and the first controlled encoder, the information inputs of which are connected to the outputs of the memory block and information inputs of the first group of the first data code converter that controls the input of which is the input of the device's list pickup and connected to the control input of the switch, the device's mode setting input is connected to the first control input of the first controlled encoder, The informational outputs of which are informational outputs of the first group of the device and connected to the inputs of the first group of the switch, the inputs of the second group of which are informational inputs of the device, the outputs of the first group of the switch are connected to the address inputs of the memory unit, the outputs of the second group are informational the inputs of the second group of the first data code converter, the outputs of which are connected to the information inputs of the first register, the synchronization input of which is the first clock input of the device, and the output The dyes are connected to the information inputs of the memory block whose recording input is the second clock input of the device, characterized in that, in order to increase the speed of the device, a second data code converter, a second register and a second controlled encoder, the outputs of which are the information outputs of the second group of the device and connected to the inputs of the third group of the switch; the output of the end of operation is the output of the input end of the device, the control input is connected to the input of the device mode, and the information The operational inputs are connected to the outputs of the second register and information inputs of the first group of the second data code converter, the information inputs of the second group of which are connected to the outputs of the first group of the switch, the control input - with the input of the device list receiving task and the second control input of the first controlled encoder, and the outputs are connected to the information inputs of the second register, the synchronous input of which is connected to the second clock input of the device, the recording enable input is connected to the output of the end of the first the controllable encoder, and the setup input to the one state is the input of the initial setup of the device. Fig, 1 V PhagZ 4 rfl About EML n FpiftlpFvflt-S FMjfl- mRGfvi- yR & wl: qpRWFig .5