SU1695287A1 - Device for information input - Google Patents

Abstract

This invention relates to information input means recorded with elevated. Noise immunity on a movable magnetic carrier, in a computer and other devices. The aim of the invention is to increase the reliability of the input information by separating its K-fold coincidence from m identical received words. The device contains information inputs 1, first 2 and second 3 amplifiers, first 4, second 5 and third 6 elements AND, first element OR 7, group of elements AND 8, switch 9, first 10 and second 11 delay elements, second element OR 12, counter 13, the first 14 and second 15 triggers, a group of shift registers 16, the majority logic block 17, register 18, the fourth element And 19, the third delay element 20, the input 21 of the initial installation of the device. 1 il.

Description

The invention relates to information input means recorded with enhanced noise immunity on a movable magnetic medium in a computer and other memory devices.

The aim of the invention is to increase the reliability of the input information.

Diagram of the device shown in the drawing.

The device contains information inputs 1 (outputs of magnetic reading heads), first 2 and second 3 amplifiers, first 4, second 5 and third 6 elements AND, first element 7 OR, group of elements AND 8, switch 9, first 10 and second 11 delay elements , second element OR 12, counter 13, first 14 and second 15 triggers, group of shift registers 16, majority logical block 17, register 18, fourth element AND 19, third delay element 20, initial setup input 21.

The device works as follows.

Each word on the media, such as a tape, is recorded in a sequential code on two tracks, with zero bits on one track, but in the form of single signals, and on the second track, single bits of the word are also represented by single signals. Let, for example, the signals from the zero-bit track, read by the corresponding playback magnetic head, go to the first reproduction amplifier 2, and the single-bit signals to the second reproduction amplifier 3. The sign of the beginning of each word is fixed by a single signal in parallel on each of the tracks. This feature is recognized by the And 4 element. Each information word, to increase the reliability of recording and reproducing, is recorded m times.

According to the initial setup signal received at input 21, the device switches to the initial state, in which all

the registers 16, the register 18 and the counter 13 are zeroed, the D-flip-flop 14 switches and blocks the AND elements 6, 6 with its zero signal, and a single signal enables the operation of the AND element 19. At the first output of the switch 9 a single signal appears. Thereafter, a starting signal is received from the computer to move the magnetic carrier, information from which is read by the magnetic heads and transmitted to amplifiers 2 and 3 (the circuits mentioned are not displayed in the diagram).

Suppose that when writing, the data array starts with (t − 1) zero words. In this case, with the appearance on the moving carrier of the sign of the beginning of the first (t-1) zero words at the output of the element And 4, a corresponding single signal is sent by which the second output in the switch will open. A single signal at this output of the switch unlocks the element AND 8 in the circuit at the input of the synchronization signal (shift) of the second of the registers 16. The output signal of the element 4 with a delay in element 10, which is slightly longer than the duration of the single write pulse signal, switches the trigger 14 with a single signal of which elements 5. and 5.6 are unblocked and element 19 is blocked. But before this, the single signals of the sign of the beginning of the first zero word complete their action, the state of the trigger 15, etc., and this will not change, and its output signal tanets zero. This trigger remembers the number of the track from which the zero or single signal is read, and converts the single image of the zero signal (transmitted through amplifier 2) to the output zero level. The output signal of the trigger 15 is fed in parallel to the inputs of all the shift registers 16, in each of which the same word is repeatedly written, repeated on the medium m times. Such registers m by the number of repeated words. As the signs of the word start appear, the switch 9 switches sequentially and unlocks the corresponding element AND 8 of the group, skipping the clock signal of the corresponding shift register 16 of the group. This signal is generated by the element 11 with a delay relative to the switching time of the trigger 15, the switch 9 and the establishment of the corresponding signals of these elements. As the carrier moves on the opened And 5, 6 elements, single signals appear that switch the trigger 15 to the zero or one state, respectively, and through the OR 7 element with a delay in the element 11, the input to the write and shift signal

through the corresponding open item

. And 8. Delay element output

11 is simultaneously transmitted to the input of the counter 13, which fixes the length of the n-bit of the bottom word. After the n signals arrive at this counter by its overflow output signal, trigger 14 switches, and elements 5, 6 are again blocked, and element 19 is opened. With the appearance of the next sign of the beginning of the current word, the described process of sequential recording of this word repeats, but next register 16 groups. With an erroneous one5 time recording of two units on both tracks, until the end of the word recording, the switch 9 will not switch, since AND 19 turns out to be a blocked zero signal from the inverse output of the trigger 14.

0 This thereby localizes the error and increases the noise immunity of the data. The output signal of the trigger 15 is determined by the input signal at its priority input. In the manner described, the same word of the array is repeated sequentially in register 16, repeated m times. The appearance of a single signal at the last output of the switch 9 with a delay in the element 20 necessary to shift the word

0 in the m-th register 16 and the establishment of signals at the outputs of the majority logic block 17, the signal from the output of the element 20 is fed to the input to write the number to the output register 18 of the device. The majoritarian logic block 17 is designed to correct errors by allocating K and more than once repetitive values each m times recorded in registers 16 of the group of bits of the same word.

0

Claims (1)

Claims An information input device comprising a counter whose reset input is the input of an initial installation 5 devices, characterized in that, in order to increase the reliability of the input information, the first and second amplifiers are introduced into it, first to fourth elements are And, the first and second elements 0 OR, AND group, switch, first to third delay elements, first and second triggers, shift register group, majority logical block, register, amplifier inputs are 5 information inputs of the device, the output of the first amplifier is connected to the first input of the first element I and the first input of the second element I, the second input of which is connected to the second input of the third element I and the direct output of the first trigger, the inverse output of which is connected to the second input of the fourth element And, the first input of which is connected to the input of the first delay element and the output of the first element And, the second input of which is connected to the output of the second amplifier and the first input of the third element And whose output is connected to the second input of the first element OR, the second installation input of the second trigger, the first installation input of which is connected to the output of the second element AND and the first input of the first element OR, the output of which is connected to the input of the second element that delay, the output of which is connected to the first inputs of the AND elements of the group and the clock input of the counter, the overflow output of which is connected to the first input of the second OR element, the second input of which is connected to the reset inputs of the counter, switch, register and group the shift registers, and the output is connected to the reset input of the first trigger, the setup input of which is connected to the output of the first delay element, the output of the fourth element I is connected to the clock input of the switch, the output group of which is connected to the second inputs of the corresponding elements of the group, and the last output of the switch group is connected with the input of the third delay element, the output of which is connected to the clock input of the register, the outputs of which are the information inputs of the device, and the information inputs are connected with the outputs of the majority logic block, the inputs of which are connected in parallel with the outputs of the corresponding shift registers of the group, the clock inputs of which are connected to the outputs of the corresponding elements of the AND group, and the information inputs are connected to the output of the second trigger.