SU1691847A1 - Systolic processor - Google Patents

Abstract

The invention relates to computing and can be used in automated data processing systems operating in real time. The aim of the invention is to increase the performance of the systolic processor by ensuring conflict-free data exchange between computational modules. The goal is achieved by introducing K + 1 exchange devices into a systolic processor containing K compute modules. 1 hp f-ly, 4 ill.

Description

The invention relates to computing and can be used in automated data processing systems operating in real time.

The purpose of the invention is to increase the performance of the systolic processor by ensuring conflict-free data exchange between computational modules.

FIG. 1 shows a block diagram of a systolic processor; in fig. 2 is a block diagram of an exchange device; in fig. 3 is a control block (exchange) diagram; in fig. 4 is a diagram of a computing module.

The systolic processor (Fig. 1) contains the first 1 and second 2 clock inputs, information input 3, the first inputs 4-7, respectively, of the signs of a write to the memory, read from the memory, write to the counter and read from the counter, reset input 8, the third a clock input 9 (K + 1) of exchange devices 10, K computing modules 1V, interrupt inputs 12, transition control inputs 13, download indication input 14, write permission input 15, read permission input 16, program memory access enable output 17, external data bus input / output 18, synchronization output 19, output 20 reading strobe, write strobe output 21, address output 22, data input / output 23, information output 24, second inputs 25-28, respectively, of the characteristics of writing to the memory, reading from the memory, writing to the counter and reading from the counter.

Each exchange device 10 (FIG. 2) includes registers 29-32, a memory unit 33 and a control unit 34.

The control unit 34 (FIG. 3) contains AND-HE elements 35-37, buffer amplifiers 38 and 39 with a three-stable output, switch 40, counters 41 and 42, And 43 element, AND-NE elements 44 and 45. And 46 element the element AND NOT 47, the element AND 48, the inverter 49, the six nodes of the pulse formers 50i-50c, each of which consists of the element AND 51, the triggers 52 and 53 and the element AND-NOT 54.

cl

with

oh che

00

N

Vj

Each computational module 11 (FIG. 4) constitutes amplifiers 55 and 56 with a three-stable output, microprocessor 57, amplifiers 58 and 59 with a three-stable output, elements OR 60 and 61, decoders 62 and 63, element AND 64, memory 65 and element OR 66.

The systolic processor works as follows.

First, the processor is configured to solve the problem. The adjustment is made by loading into memory 65 of each computing module 11 of the respective programs. Each program loaded into the computing module 11 is part of a general problem solving program. In memory 33, the first exchange device 10 from output 3 loads the first input data array and control information accompanying the array. The control information indicates the problem code to be solved, the starting address, the dimension and state of the array. If the cell of the memory block 33, which defines the state of the array, contains zero, this means that the data array is not loaded in the memory block 33, if one, it means that the data array is loaded and ready for processing. The control information is recorded in the determined addresses of the memory unit 33. The storage space of block 3 of each exchange device 10 is determined by the size of the data files being processed and their control information. The minimum size of the memory block 33 should provide storage of two maximum data arrays with their control information.

Before starting, the first data array and its control information are loaded into the first area of the memory block 33 of the exchange device 10i, and in the cells determining the state of the two memory areas, one and zero are recorded. Zero zeros are written in the cells that determine the state of the memory block 33 of the device 102-1 OK-and exchange. When the unit is installed at input 8, the processor stops and runs to execute the programs recorded in memory 65 of the computational modules 11. In At the beginning of operation, each computational module 11 analyzes the cells determining the state of the block 33 of the memory of the exchange devices 10. If zero is written in these cells, then the corresponding computational modules 11 are switched to the idle mode, and if the unit is, then to the array processing.

4In the beginning of the processor, the first computational module 11, based on the results of the analysis, proceeds to processing the array,

the memory block 33 recorded in the first region, and the computational modules 112-11k in the standby mode. The first computing module 11 reads the code of the problem to be solved.

and proceeds to the solution of the first part of this problem over the data recorded in the first area of the memory block 33. The results of solving the first part of the problem by the computing module 11 are recorded in the first

the area of the memory block 33 of the second exchange device 102. The results of processing the input array by the first computing module 111 are input to the second computing module 112. Together with

data into memory block 33 of exchange device 102 is recorded by its control information. Upon completion of processing the first input array and loading the results of its processing into the first area of the block 33

the memory of the exchange device 102, in the cells of the state of the data of the areas of the memory block of the first 10i and the second 102 of the exchange devices, respectively, is written zero and one. Simultaneously with array processing

From the first area of the memory block 33 of the exchange device 10i, the second data array with its control information is loaded from the input 3 to the second area of the memory block 33 of this exchange device. At the end of loading information into the second area of the memory unit 33 of the exchange device 10i, a unit is recorded in the state cell of this area of the memory unit 33. Upon completion of processing the first array

data and loading of the results of this processing into the block 33 of the memory of the exchange device 102, the computing module 111 enters the standby mode. In idle mode, the computational modules 11i-11x are

until the interrupt signal arrives at the inputs 12i, 1221-2k. The period of arrival of interrupt signals is equal to or greater than the required time for solving any 1st part of the task and coincides with the period of arrival.

into the data array processor. The processor is synchronized by interrupt signals, i.e. operates at a forced rate with a cycle equal to the period of arrival of the interrupt signals.

At the beginning of the next clock cycle, each computational module 11 analyzes the cells that determine the state of the block 33 of the memory of the exchange devices 10, and, depending on the information recorded in them, proceeds to processing or waiting. In the second cycle, the first 111 and second 112 computational modules switch to processing arrays of data, and the computational modules go to standby mode.

Computing modules 11i and 112 read the code of the problem to be solved and proceed to solving the first and second parts of the problem. Computing Module 11- | processes the data from the second region of the memory block 33 of the exchange device 10i and the results of this processing loads into the second region of the memory block 33 of the exchange device 102. At the same time, the first area of the memory unit 33 of the exchange device 10i is loaded from the input 3 of the next array. When processing the second input array, the computing module 11i uses the second regions of the memory block 33 of the 1Ch-102 interchange devices. Computing module 112 processes data from the first area of the memory block 33 of the exchange device 102 and loads the results of this processing into the first area of the memory block 33 of the exchange Yuz device. Before the third processor cycle, in the first area of the memory block 33 of the exchange device 10 there is a third input array with control information, and in the second and first areas of the memory block 33 of the second 102 and third Uz exchange devices, respectively, data arrays with control information are recorded for the next work cycle. In subsequent cycles, the processor is similar to that described.

Claims (2)

Claim 1. Systolic processor containing K computational modules, characterized in that, in order to improve performance by providing conflict-free exchange, (K + 1) exchange devices are inserted into it, the first and second clock inputs of the processor are connected respectively to the first and the second clock inputs of all the exchange devices, the attributes of the record to the memory, the reads from the memory, the write to the counter, the readings from the processor counter are connected to the same first inputs of the first exchange device, in q processor reset — with the reset inputs of all computing modules, the third clock input of the processor is connected to the synchronization inputs of the computing modules, the information input-output of the processor is connected to the first information input / output of the first exchange device, the first outputs of the write-to-memory signs, readings from the memory , records in the counter, readings from the counter of the 1st computing module (1 1, 2, ... K) are connected respectively with the same inputs of the j-ro exchange device (j 1,2, ..., K + 1), second outputs , read from memory, write to counter, read from the counter of the 1st computing module are connected respectively to the inputs of the same name (j + 1) -ro of the exchange device, the information input-output of the i-ro computing module is connected to the second information input of the j-ro exchange device and the first information input-output ( j + 1) -ro exchange device. 2. The processor under item 1, which is different in that the exchange device contains four registers, a memory unit and a control unit, with the first and second clock inputs of the exchange device being connected to the same inputs of the control unit, the outputs the addresses and the sign write / read are connected to the same-named inputs of the memory block, the informational input-output of which is connected to the same-name inputs of the first and second registers and the outputs of the third and the fourth register, the information output of the first register is connected to the same input of the third register, the first information input of the control unit and is the first information output of the exchange device, the information output of the second register is connected to the same input of the fourth register, the second information input of the control unit and is information the output of the exchange device, the first inputs of the attributes of the write, read, write to the counter, read the counter of the device connected to the same inputs of the control unit, the second inputs signs of writing, reading, writing to the counter, reading the device’s meter are connected to the second inputs of the control unit of the same name, the first and second outputs of the control unit are connected to the same inputs of the third and fourth registers, respectively; the reset inputs of the first and second registers are connected respectively to the first and second inputs indications of readout of the control unit, The first and second synchronization outputs of which are connected respectively to the same inputs of the first and second registers, the synchronization inputs of the third and fourth registers are connected respectively to the first and second inputs of the records of the control unit. - to / OE f CJGO C4J O3 3 f ge L7. CXJ to Yu feg fO si 3 S th "I d- W four