SU1688205A1 - Method of determining place of failure of power and communication transmission line - Google Patents

Abstract

The invention can be used to determine the location of damage on power lines and communications. The purpose of the invention is to achieve increased sensitivity in the determination of damage with high transition resistance. The method is based on repeatedly probing the line with voltage pulses, receiving reflected pulses, storing the voltage values from the line for each time delay value, successive n-step subtraction-gain conversion for n + 1 cycles of instantaneous voltage values for each delay time, averaging output voltage of the nth stage after the n + 1 cycle of memorizing its average value. A p-step conversion of the instantaneous value of the voltage subtraction-amplification is provided for each value of the voltage after the effect of the destabilizing factor. The location of damage is determined by a non-zero subtraction result. At the same time, the number of p steps and the gain factor k of the subtraction-gain conversion stage are selected from the conditions for providing a given sensitivity according to the formula given in the description of the invention. 1 hp f-ly, C Il. about $ (/ s

Description

The invention relates to a pulse technique and electrical measurements and can be used to determine the place of damage with high transient resistance in power lines and communications.

The aim of the invention is to achieve a given sensitivity in determining damages with high transient resistance by isolating an additional p-step transformation, subtraction-amplification of instantaneous values

impulse response when repeatedly probing a line before a destabilizing factor acts on the line, the same n-step conversion of the impulse characteristic after a destabilizing factor and subtracting the memorized averaged results of these transformations before and after the destabilizing factor, and also and the gain factor k of the subtraction-gain conversion stage

ABOUT

oo oo yu

SL

15

20

25

choose from the conditions of providing zananny sensitivity.

Lig.1 shows a device for the implementation of the proposed method, - a; Fig. 2 shows the graphical dependence of the successive three-step transformation of the impulse response subtraction-amplification to the effect of destabilizing voltage for the delays t4, t, tj, tfc; FIG. 3 shows the transformed impulse response for the same delays after exposure to destabilizing voltage; FIG. k is a differential analog impulse response on the display screen.

Damage corresponds to line delay t.

The essence of the method is based on repeatedly probing a line with voltage pulses, receiving reflected pulses, memorizing voltage values from the bus for each value of the time delay, acting on the line insulation by a destabilizing factor, subtracting the voltage values from the line corresponding to the same time delay values relative to the moment of sounding, whereby the instantaneous values of the voltage for each value of the time delay are converted into a series of voltages by means of an n-step sequence For a subtraction-gain conversion during n + 1 cycles, the output voltage of the nth stage n + 1 cycle for each delay time is averaged and its average value is memorized; after the destabilizing factor is applied, the instantaneous value for each delay time is transformed into a series of voltages by p-step conversion subtraction-amplification, subtracting from the input voltage of each conversion stage the previously recorded voltages for each stage before the destabilizing factor and. the results of the subtraction at each stage by k times, the output voltage of the nth stage for each time value of the stop; ki are averaged and remember its average value.

Memorized averaged n-step conversion results before and after exposure to destabilization-30

35

40

45

50

55

five

0

five

0

five

0

five

0

five

for the same delays, the subtractive factor is subtracted and the damage location is determined by the delay time of the non-zero subtraction result

The number of steps n and the gain factor k of the subtraction-gain conversion step are selected from the conditions for providing the specified sensitivity.

A device that implements this method contains a probe pulses generator 1, an instantaneous voltage sampling device 2 for each delay time, an n-step converter 3 instantaneous values of subtraction-amplification voltages, an averaging circuit k, and an analog-to-digital converter 5 (ADC ), micro microcomputer 6, memory block 7, digital-to-analogue converters 8-10 voltages, indicator 11, switch 12, destabilizing voltage source 13.

In this case, the first output bus of microcomputer 6 is connected respectively to the generator 1 of probe pulses, device 2 sampling instantaneous voltage values, to the third inputs of the n-step converter 3, the second control bus of microcomputer 6 is connected to memory block 7 and indicator 11, bidirectional The bus links the microcomputer and the memory unit 7 with unidirectional buses, the memory unit 7 is connected to digital-to-analogue converters 8-10 voltages, the outputs of which are connected to the inputs (p-steps) of the n-step converter 3, generator output 1 pulsing pulses connected to the first input of the switch 12 and the input of the device 2 sampling instantaneous, voltage value, the output of which is connected to the first input of the first stage of n-step converter, whose output of each previous one, starting from the first, stage is connected to the first input of the next, and the output of the n-th stage, which is the output of the n-step converter 3, is connected to the input of the averaging circuit 4; the output of which is connected to the input of the analog-digital converter 5, the output of the ADC 5 is unidirectional bus connected to the mic roa 6, the second input of the switch 12 is connected to the output of the source 13 destabilizing

S1

voltage, the output of switch 12 is connected to the monitored line.

The device works as follows.

The probe pulse generator 1 through the switch 12 sends probe pulses to the line.

The device I sampling the instantaneous voltage value for each for each delay time set by the microcomputer 6 converts the instantaneous value to a constant voltage proportional to it. This voltage is applied to the first input of the first stage of the n-step transducer.

razovatel 3 subtraction-gain. The operation of the n-step converter 3 is performed in n + 1 cycles after each probing of the line for each delay time.

In the first cycle, the voltage (t1 goes to the first input of the n-step converter and passes without a change to the output of the n-step converter, since, in this case, the microcomputer sets the voltage of each step U t - U DJ and O on all its second inputs and the gain of each stage is equal to one.

The chip passes through the averaging scheme k, without change, to analog-to-digital converter 5. Microcomputer 6 sends the code M3H1 (tj) to the first array of memory block 7, MZN.

I

In the second measurement cycle, the MZN code

from the first memory array M (t), by the microcomputer resolution signal 6, enters the first digital-to-analog converter (DAC) 8, and the code M4 is received at its N inputs (N-bits), where t is the number of units of the least significant bit Yes.

Output D / I Voltage

M. (- t, T - gd - ypr arrives on the second

the input of the first stage of the subtraction-gain conversion. The signal from the microcomputer sets the gain of the first stage, equal to k. When the first step of the voltage reaches the first input, it subtracts the voltage Mdlzy and the memorized

..M "Unp TUDD

R + i

 (C

WH2

M-OJnp) +

,

also gain i, 1 k UUWlH k + m. k Unp P

Through the remaining steps of the n-step converter and the averaging circuit, the value of & k passes without change in ADC 5, is converted into a digital code Mz (t) and through multiplex

The microcomputer 6 is fed into the second array of memory block 7 A, k (t,) for each delay time A, k.

In the third measurement cycle, for each time delay of the microcomputer resolution signal 6, the M and M codes from the first and second arrays of memory module 7 of the MSN nA, -k are received, respectively, in the first and second digital-5 converters 8 and 9, so that Outputs of the first and second DAC 8 and 9 are set by

thirty

IT - Ml-I-m .IT iufp

Mg - m

and

etc

When UWJ4 enters the first input of the first stage of the converter, the subtraction-amplification operation is performed in the first and second stages of the converter, connected in series.

In the first stage: subtraction:

five

l ;.

"3 and b u

 and

raUnp. I UMSH

meke

tnUitp 2H s

-

gain

A -k L -k +

MZN

mkUcp 2N

in the second stage:

4, - og –A

Mem

k +

mkUnp -2N

L G im9ng

M 2N

Unp

Mg - mt.i

Unp (ini1) ffi

2 "

& 2 k with (m +

0-k

Through the remaining stages of the p-step converter and the averaging circuit, the u-k value passes unchanged in the A / D converter 5, is converted to the digital code Mj (t;) and through the multiplexer of the microcomputer 6 enters the third array of the memory block 7 for each delay time.

In the fourth cycle of measurement on the microcomputer signal, three stages amplify the input signals with a gain factor k; the second inputs of the three stages are supplied from the nepsoroj of the second and third DAC 8-10 of the voltage Ub U4, U3:

16882058

 k - MЈ is the result of the transformation of the second cycle; Dp k - MPi is the result of the transformation of the n-1 cycle;

D -k - Mn - the result of the conversion of the n-th cycle.

Of these codes, analog values 1 are generated at the outputs of the D / A converter 8-10,

to Ufc i.Un-1 used for subtraction in the appropriate steps:

15

U

V

Etc

- in the first stage in the second and subsequent cycles;

  m

Uz in VT ° P ° th stage in the third and subsequent cycles;

nth stage

And - U Vi 2N sp

- at

 M (Unj mUry ul 7Y n

Mg-Uirp mUnp U2 3

Mj | USP U3 2N 2N

The amplification-subtraction operation is performed in three steps:

   V k Ј2.k (- U) -k,

A3 k (& 2-k - U3) -k

The value of A3 k, as described, is recorded in the fourth array of the memory block as a code.

In the n + 1 cycle of the subtraction-amplification operation, the instantaneous voltage value is applied to the input of the n-step converter in the n-steps:

 M - t ,, U «p 1

n -), and

 ig. 2n,

"" -Ґгв - h

Thus, codes for each delay value are stored in the array of memory block 7:

MZN - M - the result of the transformation of the first cycle;

U

V

Etc

- in the first mortar

neither in the second and subsequent cycles;

  m

Uz in VT ° P ° th stage in the third and subsequent cycles;

nth stage

And - U Vi 2N sp

- at

,} n + 1 and subsequent cycles.

In the array of the MZN memory unit, the code MZN - M is stored - the code of the instantaneous voltage value in the first

sounding cycle. Since all subsequent values of the MS for the same and 1 of the same delay value in subsequent conversion cycles cannot differ from each other more,

than within the stability of the parameters of the probing signal, the number m is chosen from the condition

m P

, zoid

N-H and M} And, 30 cd

With this choice of the number m, the voltage U, j, subtracted from the instantaneous voltage values (MZN) in all sounding cycles, is always less than MZN:

l - and

M i -m

  at

(

U, with (M3H6-jJ) Mg. - t

Similarly

ig

2M

Ypres. At

U 0 at Mg $ t, etc. Thus, for each delay time, signals exceeding a specified value are successively limited by the value, and. .., and ", and are amplified, and signals that do not exceed a specified value

mil pЈ 2 "

, the successors are amplified in each stage until the amplified input signal exceeds a predetermined amount, and then the amplified signal is limited and amplified again. similar to that described.

The output voltage of the nth stage An-k is averaged by circuit k during the next L-cycles set by microcomputer 6, and the average value is written to the n + 1 array of memory block 7 for each delay value as M (tj) codes.

The averaging scheme A during the first n cycles is the buffer cascade, during the subsequent L cycles of averaging it is the accumulator of the n + 1th cycle being the first of the L-C averaging. The output voltage of the circuit in each of the n-cycles and the last L-cycle is fed to the A / D converter 5 by the control signal from the microcomputer 6.

After that, the switch 12 disconnects the line from the probe generator and connects it to the source 13 of the destabilizing voltage. After destabilization of the transition resistance at the site of damage, switch 12 again connects the line to the probe pulse generator. The device operates for another L clock cycles for each delay time, during which circuit k averages the output voltage of the nth stage of the n-step converter 3 when installed at its second inputs using control at its second inputs using the microcomputer control 6, respectively, of the stresses U, U, ..., Uh for each flag of the delay. This averaged voltage is converted by the ADC 5 into a code,) which for each delay time is compared with the code „(M) extracted from n + 1 of the memory block array DN b. If there is no damage, indicator 11 does not fix the damage.

In the presence of damage for the delay tK, after averaging, the voltage value is converted into a code

Vk l, 1

M (p.L + MG

where Lo is the change in instantaneous value due to destabilization of transient resistance;

Mq is a digital code of the value Yes-k, indicator 11 fixes the damage for the delay tk by the difference of the compared codes equal to Ma. Detection condition for high leakage:

m Unp i, And „m-k Unp

2N u4 k 7

. m-Unp ug

As 28rbC2N-m.k)

(2H-n-k)

For delays t ,,, t - UM, H (t), Uwp (t) (figure 2) exceeds the specified value

tm m U.np U3 i

For delays t, tn - VM1 (t), U (tK) is less than the specified value

m Unp „

U, --- oTi therefore for them U 0.

To delay t the value of ut-. Less than a given value of U

m Ufip -r-fj, therefore for it and U Ib

 - IMZD K)

After exposure to destabilizing voltage and comparison of codes uj-k, damage was detected to delay t.

With the known element base of an ADC and DAC (N 10), this expression allows choosing the number of conversion stages to provide a given sensitivity based on the difference of the reflection coefficient

h

dr „

 and

Zoid

where DRD is the difference between the reflection coefficients before and after destabilization of the transient resistance;

U is the change in the instantaneous reflection value from damage due to stabilization;

and ...... amplitude .uning

Nala

For a given sensitivity of the DS, it is possible to determine the parameters k, n of a p-step converter subtraction-gain1

fr (1 m k

Given the parameters k, n of the p-step converter subtraction-amplification, it is possible to determine the achievable sensitivity.

Pg ™ 0 Oe

m k -. - -pp),

510ID tip

when n 2, m, U k 10 5-1; G7. d P3: 5 I j t. with a two-step transformation of the impulse response subtraction gain, sensitivity is achieved to high-resistance damages of the order IG6-1 (G5 (1GNY2) dB), with a 3, n 5, N 10, k 10g, 51 (P, i.e., with a three-step transformation With the gain of each step k 1UU, the sensitivity of CG7-1СГ8 (1st (LOBO dB)) can be achieved.

With a four-stage transformation on the same element base (N 10), a sensitivity of 1P - U, (180-200 dB) 5 -1C- 1 D Р 5-10 9 can be achieved.

Such sensitivity allows detection of leaks (damages with high transient resistance) of the order of 1UO kOhm - UIO M (V with a change in the resistance of the leak during destabilization by 1-2%.

The use of a predetermined method for determining the location of a damage that provides a given sensitivity: allows one to determine the distance to damage with a large transient resistance with a high degree of probability. This method does not require conventional energy-intensive equipment to reduce the transient resistance (burner devices, breakdown installations, etc.). Therefore, detection is necessary, damage

five

0

five

0

40

35

five

Using the proposed method, it is more economical both with glasses to reduce energy consumption and shorten the time for damage search and repair, which does not require significant cable damage.

Claims (2)

1. The method of determining the location of damage to power lines and communications, based on multiple probing of a line by voltage pulses, receiving reflected pulses, storing voltage values from a line for each time delay value, acting on the line insulation by a destabilizing factor, subtracting voltage values from lines corresponding to the same values of the time delay relative to the moment of the probe, the determination of the damage location by the time delay, characterized in that, in order to achieve In order to determine the damage with high transient resistance for each value of the time delay, n + 1 + L samples of the instantaneous values of the voltage from the line are formed, the instantaneous values of the voltage for each delay time are transformed into a series of voltages by n-step sequential conversion subtraction -the gain for n-H cycles, and the conversion results for n cycles are reduced by a specified amount, the same for all cycles, remember the reduced conversion result or zero, if the result of the conversion is less than a specified value, for its further subtraction from the input currents corresponding to the step, while the result of the n-step conversion memorized in the first cycle is subtracted from the instantaneous value of the voltage from the line in the first conversion step, BO second and all subsequent cycles, remembered in the second cycle, the result of the second n-step conversion is subtracted from the output voltage of the first stage, in the second conversion stage B of the third and subsequent cycles, by writing the result of the nth step transformation, which is given in the nth cycle, is subtracted from the output n-1 stage in the n-th conversion stage in the n + 1 cycle, with this gain increasing sequentially from cycle to cycle, increasing it in the first cycle conversion equal to one for all steps of the conversion, equal to k in the first step in the second cycle, equal to k in the first and second steps in the third cycle, equal to k in all steps of the n-step conversion in n + 1 and subsequent L-cycles, current L cycles instantaneous value of voltage Each time delay is subjected to n-step conversion subtraction-gain during one cycle, subtracting from the input voltage of each conversion stage the memorized voltage for each stage, the output voltage of the n-th stage n + 1-st and subsequent cycles for each time the delays are averaged over the L-cycles and (the averaged instantaneous values of the voltages for each value of the delay after the effect of the destabilizing voltage are remembered the instantaneous value for each time (the delays again The n-step atomic subtraction-gain conversion for n + 1 cycles, the conversion results of n cycles decreasing by a specified amount, the same for all cycles, remember the reduced conversion result or zero if the conversion result is less than the specified value for subsequent subtraction from the input the voltage of the corresponding step, while the result of the n-step conversion memorized in the first cycle is subtracted from the instantaneous value of the voltage in the first conversion step in the second and all subsequent cycles, a memory in the second cycle the second result 5 0 5 Q five 0 five first n-step conversion is subtracted from the output voltage of the first stage, in the second conversion stage in the third and subsequent cycles, the result of the n-th conversion step that is memorized in the nth cycle is subtracted from the output voltage of the n-1 stage in the nth stage conversion in n + 1 cycle, while the gain sequentially from cycle to cycle is increased, set it in the first conversion cycle equal to one for all stages of conversion, equal to k in the first stage in the second cycle equal to k in the first and second stu En x in the third cycle, equal to k in all steps of the n-step transform in n + 1 and subsequent L-cycles, during L-cycles, the instantaneous voltage values for each delay time are subjected to n-step conversion subtraction-amplification one cycle, trying to remember the input voltage for each stage from the input voltage of each conversion stage, the output voltages of the nth stage n + 1 and subsequent cycles for each delay time are averaged during L-cycles and its average values are memorized remember s results averaged n-converting step before and after exposure to a destabilizing voltage for the same subtracted delays and determining location of damage on the delay time of occurrence of non-zero result of the subtraction. 2. The method according to claim 1, characterized in that the number of n steps and the gain factor k of the subtraction-gain step of the conversion are chosen from the conditions for providing the specified sensitivity NJ € and tl t, t, B ffr fft ffj o t