SU1688173A1 - Device for measuring average value of amplitude of steady-state voltage - Google Patents

Abstract

The invention relates to electrical measurements and can be used in amplitude values of voltmeters and systems for assessing the quality of electrical energy of mobile power sources for measuring the established voltage values. The purpose of the invention is to improve the measurement accuracy of the amplitude voltage, achieved by using the measuring transformer 1 of the analog-digital converter 2, three digital comparators 4-6, block 7 of the code comparison, the register 8, the register 9 of the third, fourth, fifth counters 13, 12 , 25, three differentiating circuits 15-17, two logical elements NOT 18, two logical elements AND 19, 20, a pulse divider 29, a decoder 23, a Reset bus 26 and an electronic switch 28, a digital reading unit 22. The device contains also limiter 3, the first, second counters 10, 11, the generator 21 pulses, indicator 24. 1 Il. sl f Hahaa

Description

The invention relates to a measurement technique and can be used in amplitude value voltmeters and evaluation systems of electrical energy quality indicators of mobile power sources for measuring the established voltage values.

The purpose of the invention is to improve the measurement accuracy of the steady-state amplitude value of the voltage.

The drawing shows the functional diagram of the device.

A device for measuring the average amplitude contains a measuring transformer 1, the output of which is connected to the inputs of the analog-digital converter (ADC) 2 and the limiter 3 the first 4. second 5, third 6 digital comparators and block 7 of code matching, register 8, which sets register 9 , first 10, second 11, third 12, fourth 13 counters and trigger 14, first 15, second 16 and third 17 differentiating circuits, first logical element NOT 18, first 19 and second 20 logical elements And, pulse generator 21, digital reading unit 22, containing a descrambler 23 Torr, the LED 24 and the fifth counter 25, and reset bus 26, the second logic element NE 27, electronic switch 28, frequency divider 29

About 00

The input signal bus through the electronic switch 28 is connected to the input of the analog-digital converter 2, the output bits of which are connected to the bits of the first input of the first digital comparator 4 bits of the input of the register 8, the bits of the output of which are connected to the bits of the second input of the first digital comparator 4, the first input of which is connected through the first differentiating circuit 15 to the synchronization input of the reshstr 8, the second output is connected to the second counter of the second counter 11 and the single input three through the second differentiating circuit a gage 14, the reset input of which is connected to the fault input of the first counter 10 and through the third differentiating circuit 17- with the output of the limiter 3, whose input is connected to the output of the electronic switch 28 and the input of the first differentiating circuit 15, and the output of the trigger 14 is connected to the third input of the first logic element;) And 19, the second input of which is connected to the output of the generator 21 pulses and the fourth input of the second element I 20, and the first input - with the y of the second logic element 1 HE 27, whose input is connected to the first input of the second element I 20 m the output of the second digital comparator 5, the bits of the first input of which are connected to the corresponding bits of the output of the register 8, and the bits of the second input - with the corresponding bits of the output of the first counter 10, the counting input of which is connected to the output of the first element I 19, and the counting input of the third counter 12, the output bits of which are connected to the corresponding bits of the first input of the fourth digital comparator, and the reset input - with the reset bus and the reset input of the first 25, fourth 13 and second 11 counters, and the output bits of the second The first counter 11 is connected to the corresponding bits of the first input of the third digital comparator 6, the bits of the second input of which are connected to the output bits of the master register 9, the first output to the control input of the electronic key 28, the second output to the third input of the second element I 20 The second input of which is connected to the output of the first element HE 18, the input of which is connected to the output of the block 7 of the matching codes, the bits of the second input of which are connected to the corresponding output of the fourth counter 13, the counting input of which united with the release of the second ele

And 20 and the input of the divider 29, the output of which is connected to the counting input of the fifth counter 25, the output of which is connected via the decoder 23 with the ramps of the input of the indicator 24.

The device works as follows.

A signal is sent to bus Reset 26. Counters 11-13 and 25 are reset. When a positive half-wave voltage appears at the output of transformer 1, a signal appears at the output of limiter 3, which is fed to the inputs of differentiating circuits 15 and 17, and pulses from them

The 5 outputs are reset by the counter 10, the register 8, and the trigger 14 is transferred to the state in which the signal disappears from its direct output.

At the same time, the signal from the output of transformer 1 is fed to the input of ADC 2, and the code from its output goes to the first input of comparator 4, where it is compared with the code coming from the output of register 8. Since register 8 was previously cleared and

5, the voltage at the input of the A / D converter 2 increases, a signal appears at the first output of the comparator 4, This signal is fed to the input of the differentiating circuit 15, and the pulse of its increased instantaneous voltage is written to the register from the pulse from its output. With a further increase, there will be a rewriting of codes in register 8 until the moment of recording the code of the amplitude value of the first half-wave. In the drop-down section on the 5th voltage, the codes of instantaneous voltage values at the output of the ADC-2 will be less than the generated amplitude code at the output of the register 8 and a signal is output at the second output of the comparator 4. The signal from the second output of the comparator 4 is fed to the input of the differentiating circuit 16 , the output from which the trigger 14 is transferred to the state at which 1 appears at its direct output. The signal at the output of com5 parator 5 is absent, since the amplitude code of the first wave of the voltage under investigation from the register 8 output is fed to its first input, and the zero code from the output of the counter 10, previously

0 zeroed out. The low level from the output of the comparator 5 is inverted by the logical element NOT 27 to 1, which is fed to the first input of the element 19. With the arrival of 1 from the output of the trigger 14 through the element 19,

5 outputs of the generator 21 to the input of the counters 12 and 10 will receive pulses. The receipt of pulses at counters 12 and 10 will stop at the moment when the codes at the output of counter 10 and the output of register 8 coincide. At this point, the signal at the output of the compa

rator 5, and at the exit of the element NOT 27 will disappear, closing the element And 19 on the first entrance.

At the time of the occurrence of the second positive half-wave of the voltage under study, counter 10, trigger 14 and register 8 are reset, the number of half-waves analyzed is recorded in counter 11, and the amplitude code of the first half-wave is recorded in counter 12.

The formation of the amplitude code of the second half-wave in register 8 occurs as described above. After the amplitude code is written, a second signal appears at the second output of the comparator 4, and the second pulse from the output of the differentiating circuit 16 is entered into the counter 11, the trigger 14 changes simultaneously, and the element 1/1 19 opens, the pulses from the generator output 21 to the input of the counters 12 and 10. At the output of the counter 12, a code of the sum of the amplitudes of the first and second half-waves is formed, and at the output of the counter 10, the amplitude code of the second half-wave is formed. After completing the generation of the codes, a signal appears at the output of the comparator 5 and the AND element 19 is closed at the first input.

At the time of the occurrence of the next wave, the register 8, the counter 10 and the trigger 14 are again reset to their initial state and everything repeats. In this case, in the counter 12, a code of the sum of the amplitudes of the half-waves is formed, and in the counter 11 - the code of the number of the analyzed half-waves.

When the number of amplitudes analyzed by the register 9 is reached, the codes at the inputs of the comparator 6 coincide. The signal at the first output of the comparator b disappears, closing the key 28 and disconnecting the input voltage, and at the second output of the comparator 6, the signal appears, preparing AND 20 for the third input. On the second input element And 20 prepared by the signal from the output element NOT 18, since the inputs of block 7 codes do not match. After the formation of the amplitude code of the last half-wave at the output of the counter 10 and the sum of the codes at the output of the counter 12, the signal at the output of the comparator 5 appears and the element 20 opens. The signals from the generator 21 start to flow to the input of the counter 13 and through the divider 29 to the input of the counter 25. The division factor of the divider 29 is set equal to the number of half-waves analyzed, set by master register 9.

At the output of the counter 25, a code of the average amplitude of the analyzed half-waves of the voltage under study is formed. Code formation is completed when the codes at the outputs of counters 12 and 13 are aligned. A signal appears at the output of the comparator 7, and at the output of the element HE 18 disappears, closing the element AND 20 at the second input.

The code of the average amplitude from the output of the counter 25 is fed to the input of the decoder 23, where it is decrypted into a convenient form and is fed to the input of the indicator 24.

Claims (1)

Claims An apparatus for measuring the average amplitude of a steady-state voltage, comprising an electronic key, a counter, a digital reading unit, a trigger, an analog-to-digital converter, a pulse generator, a code matching unit, characterized in that. in order to improve measurement accuracy, three digital comparators were entered into it, a register, a master register, three differentiating circuits, a limiter, a frequency divider, two AND elements, two HE elements, three counters, a measuring transformer, the first output of the secondary winding of which is connected to the electronic input key, the output of which is connected to the input of the analog-digital converter, the outputs of which are connected to the first inputs of the first digital comparator and the inputs of the register, the outputs of which are connected to the second inputs of the first digits a new comparator, the first output of which is connected through the first differentiating circuit to the synchronizing input of the register, and the second output through the second differentiating circuit is connected to the counting input of the second counter and the counting input of the trigger, the reset input of which is connected to the reset input of the first counter and through the third differentiating circuit - with the input of the first differentiating circuit and with the output of the limiter, the input of which is connected to the output of the electronic key, the output of the trigger is connected to the third input of the first element And, sec oh input of which is connected to the output of the pulse generator 1 by the fourth input of the second element And, and, the first input - with the output of the second element NOT, the input of which is connected to the first input of the second element And and the output of the second digital comparator, the first input of which is connected to the output of the register, and the second output - with the output of the first counter, the counting input of which is connected to the output of the first element I and the counting input of the third counter, the outputs of which are connected to the first inputs of the fourth digital comparator, and the reset input to the Reset bus, the reset inputs of the digital readout block, the fourth and second counters, the outputs of the second counter are connected to the first inputs of the third digital comparator, the second inputs of which are connected to the outputs of the master register, the first output is connected to the third input of the second element And the second input # | $ 1Rrgo is connected the output of the first element (NOT, the input of which is connected to the output of the coincidence block 0 codes, the second inputs of which are connected to the outputs of the fourth counter, the counting input of which is connected to the output of the second element I, the input of a frequency divider, the output of which is connected to the counting input of the digital reading unit, the terminals of the primary winding of the measuring transformer are connected to the input terminals of the device, and the second The secondary winding is connected to a common bus.