SU1663615A1 - Transceiver - Google Patents

Abstract

The invention relates to electrical measuring technology and can be used for remote measurement and metering of electrical and thermal energy, consumption of liquids, gases, and the like. The purpose of the invention is to improve the accuracy and reliability of the device. The device contains a shift register, a coincidence unit, a divider, decoders, counters, a block for determining the transmission and reception of information, a pulse driver, a divider for resistors, an amplifier, a clock generator, keys, filters, a decoder for the control point, and interval of transmission and reception of information, pulse shaper, keys, counter, divider on resistors, amplifier, clock generator, filters. 2 Il.

Description

The invention relates to a measuring technique and can be used to remotely measure and record electrical, thermal energy, the flow of liquids, gases, etc.

The purpose of the invention is to improve the accuracy and reliability of the device.

Figure 1 shows the functional diagram of the device; FIG. 2 shows diagrams explaining his work.

The device contains, at a controlled point, a shift register 1, a block 2 of coincidence, decoders 3 and 4, counters 5, 6 and 7, a block 8 for determining the transmission and reception interval of information, a driver of 9 pulses, a divider 10 on resistors, an amplifier 11, a generator of 12 clock pulses , divider 13, keys 14 and 15 and filters 16 and 17, on the control point, a decoder 18, block 19 for determining the transmission interval and

receive information, pulse shaper 20, keys 21 and 22, counter 23, divider 24 on resistors, amplifier 25, clock pulse generator 26, and filters 27 and 28. Positions 29, 30, 31, and 32 designate the information input, the first and second controls The device's output and output terminals, respectively, and the positions 33 and 34, the phase and neutral wires of the device, respectively.

The device works as follows.

The input of the equipment of the controlled point (CP) receives impulses from the meters of electric meters or from any other source of information represented in the number-pulse code.

The input pulses are fed to a one-bit shift register 1 and a counter 7. The output signal of the shift register 1 is Po

about you

ate

steps on the controllable key 14 and the coincidence unit 2, the clock shift pulses are generated by the generator 12 and the frequency divider 13 (Fig. 2) and are fed to the shift register 1 through the coincidence unit 2 only when two other inputs of the coincidence unit 2 are fed the same levels, the first level arrives at block 2, coinciding with the output of the shift register 1, and the second, from the output of the decoder 3. Each input pulse sets a high level at the input of the shift register 1 only when a clock pulse is received from block 2 of coincidence. In the initial state, the outputs of the shift register 1 and the decoder 3 are low and the coincidence unit 2 passes to the input of the shift register 1 all clock pulses from the frequency divider 13. Therefore, the first in order pulse of the input sets a high level at the output of the shift register, prohibiting the passage of the shift clock pulses through block 2, while the output of the decoder 3 (Fig. 2) remains low.

A signal proportional to the voltage of the electrical network is fed to the input of the unit 8 from the output of the divider 10. At one of the outputs of the block 8 (+ sign, figure 2) a high level appears with a positive voltage of the electrical network of 0.4 kV. The leading edge of this level sets the counter 5 to zero and is fed to the input of the control key 14. If the shift register register 1 is also high at the output, the signals of the pulse generator 12 close and open the control key 14 causing a phase to zero in the circuit current pulses whose frequency is equal to the frequency of the generator 12.

At the second output of block 8 (the sign -, Fig. 1), a high level appears with a negative voltage of 0.4 kV electrical network. On the leading edge of this level, the control key 15 is prepared to pass the signals of the driver 9 pulses.

The filter 17 provides a selection from the output voltage of the divider 10 on the resistors of signals of the required frequency, which after the amplifier 11 are fed to the input of the former 9. The output signals of the latter (Fig. 2) through the control key 15 are fed to the counter 5, whose outputs are excluded to the decoder inputs 3. If the number of pulses arriving at counter 5 is greater than or equal to the specified value, a high level appears at the output of decoder 3, the leading edge of which increases by one the contents of counter 6 and

allows passage through the block 2 of the coincidence of the clock pulses of the shift to the shift register 1, if the output of this register 1 (Fig. 2) at this time is also high

level. In this case, the first in order clock shift pulse from the frequency divider 13 sets the output of the shift register 1 to a low level, prohibiting the passage through unit 2 of all matches

0 subsequent shift pulses.

The impulse at the input 29 of the CP (Fig. 2), which arrived at a negative voltage of the electrical network and a high level at the output of the decoder 3, is recorded in

5 is a shift register 1, but cannot establish a high level at its output, since the coincidence unit 2 is closed for shift clock pulses. The high level at the output of the decoder 3 is removed

0 at the appearance of the next in order positive half-wave voltage of 0.4 kV electrical network. Since, at the same time, the output of the shift register 1 and the decoder 3 are simultaneously low levels,

5, the coincidence unit 2 provides the transmission of the clock pulses of the frequency separator 13 to the input of the shift register 1. Therefore, the input pulse recorded in the shift register or just received at the time of the appearance of the clock shift pulse provides a high level at the output of the shift register 1 and the procedure described transmission of information between the control and the PU is repeated.

5 The total number of pulses received at the KP input is accumulated on the counter 7. The number of pulses that received confirmations of their reception by the PU equipment accumulates on the counter 6. In normal operation of the KP and PU, the readings of the counter 7 can exceed the counter 6 readings by one while No confirmation of reception is received from the control panel. Therefore, if the readings of counters 6 and 7 match or

5 differ by no more than one, decoder 4 forms a high level at its first exit 30, which is a sign of normal operation. If the meter readings differ by more than one, a high level signal is generated at the second output 31 of the decoder 4, which is a sign of failure.

The separation of the direct and reverse channels between the CP and the PU is provided by the difference in the frequencies of the generators 12 and 26 and the corresponding passbands of the filters 10 and 27. In a similar way, the problem of simultaneous operation of several CP and PU of one 0.4 kV electrical network is solved. The output of divider 24 receives a signal in which, along with a network frequency of 0.4 kV, there are pulses with a frequency of the generator 12 of the gearbox equipment. This signal is fed to the input of block 19 and filter 27.

At one of the outputs of block 19, a high level appears with a positive voltage of 0.4 kV electrical network. The leading edge of this level sets the counter 23 to zero and prepares the control key 21 for passing the signals of the driver 20. At the second output of the block 19, a high level appears with a negative voltage of 0.4 kV electrical network. On the leading edge of this level, the control key 22 is prepared to pass the signals of the pulse generator 26.

Filter 27 extracts from the signal from the splitter 24 on the resistors signals with a generator frequency of 12 pulses of the equipment KP. These signals after amplifier 25 arrive at shaper 20, at the output of which pulses appear with a positive signal at its input. With a positive half-wave voltage of the electrical network of 0.4 kV, the pulses from the output of the driver 20 pass through the control key 21 and arrive at the counter 23.

If the number of pulses arriving at counter 23 is greater than or equal to the value specified at the output of decoder 18 (FIG. 2), a high level appears, which, with a negative voltage of 0.4 kV, allows the generator 26 to pass through a controlled key 22. At the same time, an HF signal appears in the 0.4 kV electrical network, confirming that the PU equipment has a pulse received at the control input. A high level from the output of the decoder 18 corresponds to the output signal 32 of the PU equipment. If the current pulses generated by the control key 24 (Fig. 2) in the phase-zero or phase-0.4 kV network circuit are not perceived by the driver 9, as well as in cases where the number of received pulses accumulated on the counter 5 does not provide a high level at the output of the decoder 3, the output of the shift register 1 remains high. This level necessitates a repetition of the transmission of the input pulse during the next positive half-wave of the 0.4 kV electrical network.

Loss of information is possible only in the case when confirmation of the correctness of the reception does not arrive until the next pulse at the input of the equipment KP.

Claims (1)

Invention Formula A device for transmitting and receiving information containing, at a controlled 5 point, a shift register, the information input of which is the information input of the device, the output of the shift register is connected to the first input of the first key, the first filter, the output of which 0 is connected to the phase wire of the device, a clock generator, the output of which is connected to the second input of the first key, an amplifier, an information transmission and reception interval determination unit, 5 control point - the first filter, the block for determining the transmission and reception interval of information, the first key, characterized in that, in order to increase accuracy and reliability, the first, second and third counters, the second key, the second filter, pulse generator, first and second decoders, divider, coincidence unit and divider on resistors, first, second and 5, the third terminals of which are connected to the phase neutral wires of the device and the inputs of the block for determining the transmission interval and the reception of information and the second filter, respectively, the output of the latter through 0 serially connected amplifier and pulse shaper are connected to the first input of the second key, the first and second outputs of the block for determining the transmission and reception interval of information are connected to 5 combined the third input of the first key and the input Reset the first counter and the second input of the second key, respectively, the output of the latter is connected to the counting input of the first counter, the outputs of which 0 are connected to the inputs of the first decoder, the output of which is connected to the counting input of the second counter and the first input of the matching block, the output of the shift register and the output of the clock pulse generator through the divider are connected to the second and third inputs of the matching block, respectively, the output of which is connected to the clock input the shift register, the counting input of the third counter is the informational input of the device, the outputs of the second and third counters are connected to the inputs of the first and second groups of inputs of the second decoder, c responsibly, the first and second outputs which are first 5 and the second control outputs of the device, respectively, the fourth input and the output of the first key are connected to the zero wire of the device and the input of the first filter, respectively, at the receiving point is the second filter, the second key, the divider on the resistors, clock generator, decoder, counter, amplifier and pulse shaper, the first, second and third divider outputs on the resistors are connected to the phase, neutral wires of the device and the inputs of the block for determining the transmission and reception interval of information and the first filter, respectively, the output of the latter through sequentially connected amplifier and pulse shaper connected to the first input of the first key, the first and second outputs of the block determining the transmission and reception of information connected to the first th entrance 0 five the second key and the combined input Reset counter and the second input of the first key, respectively, the output of the latter is connected to the counter input of the counter, the outputs of which are connected to the inputs of the decoder, the output of which is connected to the second input of the second key and is the information output of the device, the output of the clock generator is connected to the third input of the second key, the output of the second key through the second filter and the fourth input of the second key are connected to the phase and zero wires of the device, respectively. Outputs ft. w r-t G + I ± I  SHGISHPLP IiILJ .. iIchiI input 29 & -1-4-i-output i.7 i j-- y-yr Bfaffi current 44BbttOd i nnnn f /,. 20 LJUHIIU r 1Ш1ПШШГ | 4 j J iii f1 I I S & .28 Current i | A tMJIL St. 9 CT Exit | r.j i1 & -L I H -I - M n i-i g 1i ( -IH --ifflfflflf H Jlj