SU1285408A1 - Device for checking and marking cable conductors - Google Patents

Abstract

The invention relates to instrumentation technology and can be used to mark and control the cable cores. The purpose of the invention is to simplify the device by eliminating the elements of the phase-width-pulse coding and decoding the number of the controlled core and expanding the functional capabilities of the device by determining the number of short-circuited cores. The device additionally introduces a frequency divider 7, a demultiplexer 13, a counter 6 with a variable division factor keys 11.1-11.P and differentiating elements 10.1-10.p. The device also contains counters 1 and 8, decoders 2 and 9, digital indicator 3, a generator of 4 pulses, a selector 5 of a clock signal and a generator of a clock signal 12. When jcopoTKOM closure of the cable with on the latcher 3, several numbers of conductors are displayed sequentially in time, which allows opening the closure. 2 Il. cl

Description

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The invention relates to instrumentation technology and can be used to mark and control the cable cores.

The purpose of the invention is to simplify the device by eliminating the elements of the phase-width-pulse coding and decoding the number of the controlled core and expanding the functional capabilities of the device by determining the numbers of short-circuited cores.

Fig, 1 shows a diagram of the device; FIG. 2 shows timing diagrams of signals on the cable cores.

The device (Fig. 1) contains a second counter 1, a decoder 2, a digital indicator 3, a pulse generator 4, a clock signal selector 5, a counter 6 with a ri-variable-5 division factor, a frequency divider 7, the first counter B, the first decoder 9, differentiation elements 0.1-10.p, keys 11.1-1, p, g: generator 12 clock signal, emultiplexer .13,

On fi. Also shown is a test cable 14 with cores 15,, p,

The output of the 4-pulse generator is connected with the counting input of the counter 6 with a variable division factor directly, and through the frequency divider 7 with the input of the first counter

8, the connected outputs with the control inputs of the counter 6 with a variable division factor and the demultiplexer 13 and with the inputs of the first decoder 9 connected by the outputs

through the corresponding differentiating elements 10.1-10, p with the first inputs of the corresponding keys 11.1-11, p connected by the second inputs with the output of the synchronization generator 12 and the outputs with the corresponding output pulses from the generator 4 (fig 1) simultaneously enter the input frequency divider 7 with a ratio of de ni and the counting input of the counter 6 s

variable division ratio. Counter 6 allows to transfer to the output part or all of those that have arrived at its counting: input pulses, depending on the code on its control

the inputs V, Vj, ,,.,, V, as a result of which the frequency of the output pulses can vary from / n to n-1 / n (for example, the counter K155IE8),

After passing the pth pulse

From the generator 4, the first pulse appears at the output of the frequency divider 7, and at the outputs of the counter 8 having a recalculation factor n, the potentials appear corresponding to code 000,., 1, This code goes to the control inputs of counter 6, demultiplexer 13 and the decoder 9. In this case, the output of the counter 6, the demultiplexer 13 commutes with the core 15.1 of the cable to be tested 14, At the time of generating the code 000 ,,, the positive pulse at the output of the decoder 8 is formed at the outputs of the counter 8. This pulse, having passed the differentiating element 10.1, for a period of time (given by a constant time

element 10.1) opens the key 11.1 ,.

one

The clock signal of the generator 12 through the public key 11.1 during the time V is fed to the core 15.1 of the cable 14. The time of saving the code 000 ,,, 1 at the output of the counter 8 until it is changed to code 000 ,,, 10 is determined by the coefficient of (K ) dividing the frequency divider 7 and the frequency (f) of the generator 4, the values of K and f are chosen so that during the storage of the code 000 ,,, 1 at the output of the counter 8 from the output of the generator 4 by

The device's outputs connected to the co-output 45 of the counter 6 passed only one and the corresponding outputs of the demultiplexer 13 connected by an information input to the output of the counter 6 with a variable division factor. The device's input is connected directly to the counting input of the second counter 1, and through the selector 5 of the sync signal with installation 1m input of the second counter 1 connected by outputs through the second decoder 2 to the inputs of the digital indicator 3,

The device works as follows.

pulse. This impulse comes through the demultiplexer 13 following the signal of the generator 12 to the core 15.1 of the cable 14 (FIG. 2). After the pulses are formed on the core 5.1 and one from the output of the frequency divider 7, one is added to the counter 8, which leads to writing counter 8, code 000 ,,, 10, corresponding to a change in the conversion factor of counter 6 and connecting its output through demultiplexer 13 to core 15.2 cable 14, at the moment of writing code 000.,. 10 into counter 8 through key 11.2 to core 15 , 2 sets the hygial from the generator 12 and then two pulses from the generator 4 (Fig. 2). 8, the signal for each of the cores 15.1 of one signal from generator 12 and i clock signals from generator 4 (FIG. 2) is similarly implemented. The number i of pulses specified from the output of counter 6 to the input of the demultiplexer 13 during the same code storage time the output of the counter 8 is determined by code (i), which is fed to the inputs V - V of the counter 6 and determines its conversion factor. The series of pulses on the cores 15.1 of the cable 14 are periodically repeated.

To highlight the conductor number of the cable 14, the input of the counter 1 is connected to an arbitrary conductor 15.1 of the cable 14. The selector selects a sync signal from the sequence of signals on the conductor 15.1 using one of the sync signal properties that distinguishes it from other signals (amplitude, frequency, duration) and sets it to the installation input of counter 1, which is set to zero. After this, the counter 1 calculates the number 1 of pulses received at its counting input from the conductor 15.1 and sets the code of the value i via the decoder 2 to the digital indicator 3, by which the operator determines the conductor number equal to 1; when a wire is broken, the indicator of the wire number on indicator 3 is absent, which allows you to detect the wire.

In the event of a short circuit of the cores on the indicator 3, several numbers of the cores are displayed sequentially in time, which allows detecting the short circuit

The generator 12 can be a sinusoidal signal generator, then as a selector 5 it is necessary to use a band-pass filter to select and form a setup signal.

If generator 12 is a pulse generator with a duration different from the duration of the pulses of generator 4, then the selector 5 must be a pulse selector in duration and select the installation pulse from a series of pulses.

Thus, in the proposed device, in contrast to the known one, the principle of the phase-latitude-pulse coding of the conductor number is not used.

85408

the vsmeins account — h) of the location of the impregnated information pulse and its duration, which does not require complex means of encoding 5 and decoding the core number 15.1. cable 14 and greatly simplifies the device. In addition, the device will index the numbers of short-circuited wires, which expands its 10 functionality.

Claims (1)

Invention Formula Device for monitoring and marking 5 cable cores, containing a pulse generator, two counters, two decoders, a clock signal generator, a clock signal selector, a digital indicator, different 20 heme that, in order to simplify the device for eliminating the elements of the phase-width-pulse coding and decoding the number of the controlled core and expanding the functional 2-5 possibilities of the device by determining the number of short-circuited cores; a frequency divider, a demultiplexer, a counter with a variable division factor, 30 keys and differentiating elements; the output of the pulse generator is connected to the counting input of a counter with a variable division factor directly through a divider 35 frequencies - with the input of the first counter, connected with the outputs to the control inputs of the counter with a variable division factor and a demultiplexer and with the inputs of the first decipher, 40 connected exits through the corresponding differentiating elements with the first inputs of the corresponding keys connected by the second inputs with the output of the clock signal generator, 45 and outputs - with the corresponding outputs of the device, connected to the corresponding outputs of the demultiplexer, connected by an information input with the output of the counter with 50 variable division factor,. the device input is connected directly to the counting input of the second counter, and through the clock selector switch to the installation input of the second counter connected by the outputs through the second decipher to the inputs. ; digital display. " t w i