SU1679603A1 - Galvanically isolated dc amplifier - Google Patents

Description

The invention relates to an amplifier technique, in particular to DC amplifiers, with galvanic separation, The purpose of the invention is to increase the speed. DC amplifier with galva2

A physical separation contains a modulator 1, made on the first 2 and second 3 keys, an isolation transformer 4 containing the primary winding 5, the first 6 and the second 7 secondary windings, an AC amplifier 8, a demodulator 9, an output low-pass filter 15, a feedback modulator 20 , performed on the first 21 and second 22 keys, and block 23 synchronization. The goal is achieved by the fact that the demodulator 9 is made on the first 10 and second 11 comparators, the reference voltage source 12, AND 13 element. The element is NOT AND 14, and the output filter 15 is made on the first 16 and second 17 And elements, reversible. counter 18, digital-to-analog converter 19, 1 Il.

The invention relates to amplifier technology, in particular to DC amplifiers with galvanic separation.

The purpose of the invention is to increase speed.

The drawing shows the structural - electrical circuit of the proposed amplifier.

The amplifier contains a modulator 1 made on the first 2 and second 3 keys, an isolation transformer 4 containing the primary winding 5, the first 6 and the second 7 secondary windings, an AC amplifier 8, a demodulator 9 made on the first 10 and second 11 comparators, source 12 the reference voltage, the element 14 13, the element is NOT-And 14, the output low-pass filter 15, made on the first 16 and second 17 And elements, reversible counter 18, digital-to-analog converter (DAC) 19, feedback modulator 20, performed on the first 21 and second 22 keys, blo to synchronization 23, performed on the generator 24 clock pulses, the distributor 25, the trigger 26, the element 27 galvanic isolation, as well as resistors 28 and 29.

The amplifier works as follows. The generator 24 continuously generates a sequence of clock pulses, which are fed to the counting input of the distributor 25. At the outputs of the distributor 25 synchronously with the clock pulses arriving at its input, the logical unit moves from one output to another. Moreover, at any time the logical unit is present only at one output of the distributor 25. When a logical unit appears at the first output of the distribution, 1679603 A1

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The trigger 25 is set to one state and the logical unit from its first output is fed to the control inputs of keys 3 and 22. Due to this, the keys 3 and 22 open and the current flows through the second half of the windings 5 and 7.

When the next three clock pulses arrive at the input of the distributor 25, the logical unit alternately appears on the second, third and fourth outputs of the distributor 25, but the state of the trigger 26 does not change. When the fifth clock pulse arrives at the input of the distributor 25, the logical unit is set at its fifth output, which switches the trigger 26 to the zero state. A direct zero is set on the direct output of the trigger 26, and a logical unit is set up on the inverse output, which includes keys 2 and 21, so the currents start to flow through the first half of the windings 5 and 7. When the ninth clock pulse arrives at the input of the distributor 25, the logical unit is again set at the first output of the distributor 25 and the trigger 26 is again set to one and the keys 3 and 22 reopen. Similarly, in the future, the switching of the half windings 5 and 7 occurs with the keys 2.21 and 3.22.

The current flowing through the winding 7 creates in the core of the transformer 4 a magnetic flux Phos directed towards the magnetic flux F _B x generated by the input current flowing through the winding 5. The differential magnetic flux Fr = Fvh-Phos induces in the winding 5 EMF E _B x in winding 7 Δ Eos and winding 6 Δ E.

The current in the primary winding 5 is determined by the input voltage applied to the input terminals and the resistance of the resistor 28

, _ and _in - Δ e _B x

Winding 7 is a feedback winding and the current through it is determined by the output voltage of the DAC 19 and the resistance of the resistor 29

, _ and _out -Δε OS

 OS - 5Y29

EMF ΔΕ induced on the winding 6, is amplified by the amplifier 8. The output voltage of the amplifier 8 is fed to the direct inputs of the comparators 10 and 11.

The inverter input of the comparator 10 receives the reference voltage from the reference voltage source 12, and the inverted input of the second comparator 11 is supplied with a slightly lower (by 1-2 V) voltage from the voltage divider.

When the voltage on the direct inputs of the comparators 10 and 11 is less than the voltages on their inverse inputs, then logical zeros are set at the outputs of the comparators, and when the voltages at the direct inputs of the comparators 10 and 11 exceed the voltages at their inverse inputs, then logical units appear at their outputs .

For the condition of equality of magnetic fluxes in the core of the transformer 4 F _I = Phos, the equality should be

1in '71/5 ⁼ 1os' 1/77,

where ΙΛ / 5 is the number of turns of half of the primary winding 5 of the transformer 4;

ΙΛ / 7 is the number of turns of half of the second feedback winding 7 of the transformer 4.

\ Λ / ΐ9

From here 1os =! Ix yy ~.

7714

ν \ / 5

Consider the case when 1 ₀ with “1 in

In this case, F _i Pos. When a logical unit appears at the fifth output of the distributor 25 and the inverse output of the trigger 26, the keys 2 and 21 are turned on and the currents flow through the first half of the windings

5 and 7. In this half period on the first winding

6, an emf of positive polarity ΔΕ is induced, which is amplified by the amplifier 8. At the same time, Δ Ε is of such magnitude that the output voltage of the amplifier 8 is much higher than the voltage on the inverted inputs of comparators 10 and 11. Logical units are set at the outputs of the comparators. Due to this, the logical unit is also installed at the output of the element And 13. And at the output of the element NOT-14 there remains a logical zero. Therefore, the appearing single impulse at the seventh output of the distributor 25 passes through the element 16 to the input of the summation of the reversible counter 18. The content of the reversible counter 18 is increased by one, and accordingly the output voltage of the DAC 19 is increased by one discrete. The current in the second winding 7 feedback will also increase, and the EMF Δ E decreases. In the next half-period, when keys 2 and 21 are open, all processes are repeated, and this will continue until the moment of the appearance of the impulse on the seventh 5

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6

From here

during the distributor 25, the output signal of the amplifier 8 will not become less than the output reference voltage of the source 12, but there will be even more voltage at the output of the resistive divider. In this case, the output of the first comparator 10 will be a logical zero, and the output of the second comparator 11 will be a logical one. At the output of the element And 13 and the element NOT-14 there will be logical zeros, Therefore, the pulse from the seventh output of the distributor 25 will not pass through the elements 16 and 17 to the inputs of the reversible counter 18. Therefore, the reversible counter 18 will not change its state. Also, the output voltage of the DAC 19 and the current in the second winding 7 remain constant. The digital binary code from the output of the reversing counter 18 is the output binary code corresponding to the input analog voltage supplied to the device inputs and can be used directly for input into digital computers.

Analog output voltage of the DAC 19 also corresponds to the input voltage supplied to the inputs of the device.

If the input voltage decreases, then the EMF in winding 6 will also decrease: the output voltage of the amplifier 8 will decrease. If it becomes less than the voltage at the inverse input of the second comparator 11, then by the time of arrival of the pulse from the seventh output of the distributor 25 at the outputs of both comparators 10 and 11 there will be logical zeros. At the same time, a logical zero will remain at the output of the AND 13 element, and a logical one will be set at the output of the non-AND 14 element. Therefore, the pulse from the seventh output of the distributor 25 will pass through the elements And 17 to the input of the subtraction of the reversible counter 18. As a result, the contents of the counter will decrease by one. Also, the output voltage of the DAC 19 and the current through the second winding 7 will decrease by the value of one discrete. The EMF of the first winding 6ΔE will increase. In the following half-periods, everything will be similar, until the output voltage of the amplifier 8 becomes greater than the voltage on the resistive divider, but less than the output reference voltage of source 12. At a sufficiently high gain of the amplifier 8, the EMF of the first winding 6 ΔΕ required for the circuit to work is very small and tends to zero ΔΕ-> 0. Consequently, the EMF in the windings 5 and 7 Δ E _I and Δ E _O c are also small and can be neglected. Then

_ Syvh,. _ Color

"Y28 '° ^C " Pvih

Thus, the output characteristic of a DC amplifier with galvanic separation is linear.

The galvanic isolation element 27 transmits only control discrete signals for turning the keys 2 and 3 on or off. Therefore, there are no special requirements for it. The ion can be performed on optocouplers or a transformer.

A current signal can also be supplied to the input terminals, for example, from a sensor or a primary converter with a large output impedance. As a digital-to-analog converter 19, a D / A converter with a current output, i.e., a D / A converter that converts the input binary code into a current signal, can be used.

In this case, the resistors 28 and 29 can be excluded from the circuit, since the currents flowing through the windings 5 and 7 will be determined by the corresponding signal sources. The output current of the DAC in this case will be equal to

I -I

\ Λ / γ

those. the gain is determined by the transformation ratio of the transformer 4.

The inverse input of the second comparator 11 can be connected to the common wire. In this case, the second comparator 11, as well as the amplifier 8, must be powered from a bipolar power source.

The keys 2 and 3 carry out the switching of the direction of the magnetic flux, IV; by switching the input winding 5, i.e. they form an input current switch. This switch can also be performed on four keys connected via a bridge circuit. In this case, the input terminals are connected to one bridge diagonal, and the winding pins 5 are connected to the other. However, the winding 5 may not have an average output.

Similarly, the four switches connected via a bridge circuit can also have a feedback circuit switch, which in the drawing is shown made on two keys 21 and 22. In this case, the winding 7 may also not have an average output.

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Claims (1)

Claim A dc amplifier with galvanic separation, containing a modulator, made on the first and second keys, whose inputs are combined and are the input of the modulator, the outputs are connected to the terminals of the primary winding of the isolation transformer, respectively, the secondary winding of which is made in the form of the first and second windings, while the first The winding is connected to the input of an AC amplifier, the output of which is connected in series with a demodulator and an output low-pass filter, the output of which is connected to the input m feedback modulator, made on the first and second keys, the outputs of which are connected to the terminals of the second secondary winding of the isolation transformer, as well as the synchronization unit, characterized in that, in order to improve performance, the demodulator is made on the first and second comparators, the element And and the element NOT-AND, the reference voltage source, with 2 direct inputs of the comparators combined and are the input of the demodulator, the inverse inputs are connected to a voltage source, the output of the first comparator is connected to the first inputs of the AND element and the NOT-AND element, the output of the second comparator is connected to the second inputs of the AND element and the NOT-AND element, whose outputs are the demodulator outputs, and the output low-pass filter is made on the first and second elements of AND, the first inputs of which are the inputs of the output low-pass filter, and a sequence * but connected by a reversible counter and a digital-to-analog converter, and the outputs elements And connected to the inputs of the reversible counter, respectively, and the output of the digital-analog converter is the output of the device, the first and second outputs of the synchronization unit are connected to the control inputs of the first and second keys of the modulator and feedback modulator, respectively, and the third output is connected to the second inputs of the first and second elements And output low pass filter.