SU1676093A1 - Multifunctional logical module - Google Patents

Abstract

The invention relates to microelectronics and pulse engineering and can be used to implement symmetric Boolean functions of variables. The purpose of the invention is to increase the speed of the multifunctional logic module. The multifunctional logic module contains the NOT 1-1 - 1-n elements executed on MOS transistors (n is the number of arguments of the implemented Boolean functions), n + 1 alternating rus of the elements AND 2-1 - 2-10, 4-1 - 4- 6, 6-1, 6-2 and IL AND 3-1 - 3-8, 5-1 - 5-4,7,1th of which (I 1, n + 1) contains 2 (n-1 + 1) logical elements

Description

The invention relates to microelectropics and pulse technology and is intended to implement symmetrically Boolean functions (c, bf) n variables.

The purpose of the invention is to increase the speed of the multifunctional logic module.

Figure 1 shows the structural diagram of the multifunctional logic module with figure 2-6 - respectively, schematic diagrams of the NOT, two-input element AND, three-input element AND, two-input element OR and three-input element OR, respectively, in MOS-transistor elements which built module.

Multifunctional logic module with (figure 1) contains the elements NOT 1-1 - 1-5, two-input elements AND the first Rus 2-1 - 2-10, 2 (p-1) 8 three-input elements OR the second Rus 3-1 - 3 -8, 2 (p-2) 6 three-input elements AND the third Rus 4-1 - 4-6, 2 (three-input elements OR the fourth Russian 5-1 - 5-4.2 (p-4) 2 three-input elements and n Rus 6-t - 6-2, one two-input element OR Sixth Rus 7, information tires 8-1 - 8-5, n + 1 6 tuning tires 9-1 - 9-6, output bus 10.

The HE element (Fig. 2) is assembled on the load 11 and the switching 12 MOS transistors connected between the power supply buses 13 and 14. The input bus 15 of the element is connected to the gate of the transistor 12, the output bus 16 is connected to the drain of the transistor 12 (the source of the transistor 11).

The two-input element I (FIG. 3) is assembled on switching 17 and 18 and a load 19 MOS transistors connected between the power supply buses 20 and 21. The first 22 and second 23 input busbars of the element are connected respectively to the gates of transistors 17 and 18, the output bus 24 is connected to the source of transistor 18 (with the drain of transistor 19).

The three-input element And (figure 4) is assembled on the switching 25-27 and the load 28 MOS transistors connected between the power supply buses 29 and 30. First 31, the second

32 and a third 33 of the input bus element connected respectively to the gates of the transistors 25-27, the output bus 34 - with the source of the transistor 27 (with the drain of the transistor 28).

The two-input element OR (Fig. 5) is assembled on switching 35 and 36 and load 37 MOS transistors connected between power supply buses 38 and 39. The first 40 and second 41 input busbars of the element are connected respectively to the gates of the transistors 35 and 36, the output bus 42 is connected to the sources of the transistors 35 and 36 (with the drain of the transistor 37).

The three-input element OR (Fig. 6) is assembled on switching 43-45 and load 46 MOS transistors connected between power buses 47 and 48. The first 49, the second 50 and the third 51 input bus element connected to the gates of the transistors, respectively, 43-45, the output bus 52 - with the sources of the transistors 43-45 (with the drain of the transistor 46).

The proposed module works as follows.

Binary variables xi ... xs are received on information buses 8-1 - 8-5, respectively, on tuning buses 9-1 - 9-6, the tuning signals are ... or ... respectively, the values of which belong to the set {0,1}. On the output bus 10, the Boolean function F F (xi, X5) is defined symmetrically, determined by the tuning vector P (F) (L1, L1, L2, LZ, PA, L5).

According to the algorithm settings module. Let the Boolean function (sb.f.) F be symmetric essentially depends on n arguments xi, X2, ..., Xn and ai, 32Eg are the working numbers of F, where 0 is an n. Such a. B.f. usually

31 82ag

denoted by Fn. If r 1. then sb.f. Fna is called elementary (or fundamental) c.f. (esb. f.). Randomly sb.f. F F (xi, X2xn) can

be set by binary vector

L (g-) (eh), where L) is the value of F

on (any) set of values of n arguments with I units (O Ј n). Obviously, L) 1 if and only if

when K {ai, a2ag} and, moreover, has

place F l Fn ... e Fn. Consequently, the definition of the components of the tuning vector l (P) (lb,) for the implementation of some comp. F is reduced to finding such elementary cbf whose disjunction of binary numbers gives the binary number of the required function F.

Example. Find the device configuration vector for the implementation of sb.f.

F F (xl,) X1X2X3 (X4VX5) V (X1X2X3 ШхЬ vO 1Х2ХЗ) Х4Х5 (X1Х2ХЗ v X1Х2ХЗ w X1 Х2Хз) Х4 Ф $ V X1X2X3 (X4 @ X5).

As noted, given sbf can be represented as

F (xi, xs) Ls Fg L1 F L2 FЈ lz Fg

I4 Fg L5 Fg.

Moreover, binary numbers of e.s.b.f. dl have the form:

F5 ° -N5 ° - (1000 0000 0000 0000 0000 0000 0000 0000 0000); F51-N51 - (0110 1000 10000000 1000000000000000), F52-N52 - (0001 0110 0110 10000110 1000 1000 0000): F53-N53 - (0000 0001 0001 01100001 01100110 1000); F54-N54 - (0000 0000 0000 0001 0000 0001 0001 0110); F55-N55 - (0000 0000 0000 0000 0000 0000 0000 000 0001).

Binary number given sb.f.

NF - (01111110 1110 1001 fno 1001 1001 0110).

Obviously NF Ns1 N52 (/ N53 or

F (xTx5) F51 F52VF54.

Then the module settings vector for the implementation of the specified sfb. looks like l (f) (0,1,1,0,1,0).

Consequently, the signals of the logical O must be supplied to the first 9-1, the fourth 9-4 and the sixth 9-6 tuning buses, the signals from the logical 1 to the second 9-2, the third 9-3 and the fifth 9-5 tuned buses of the module.

The speed of the module, determined by the depth of the circuit, is equal to

T - (n + 2) t, where r is the delay per valve.

Claims (1)

The invention is a multifunctional logic module containing n (n is the number of arguments of the implemented boolean functions) information buses, n + 1 tuning bus and one output bus, n elements NOT, AND and OR elements on MOS transistors, input bus 1 the element NOT, () is connected to the 1st information bus of the module, which is characterized by the fact that 0 five 0 five 0 five 0 five 0 5 speed increase, contains n + 1 rus of logical elements AND and OR, the output bus of the logic element (n + 1) - r is connected to the output bus of the multifunction logic module, (2H) -th rus (IJ-jDcontains (2n-2j ±. 2 elements And, the 25th rus (S 1, -n- contains 2 (n-2S + 2) elements OR, (rM) th rus contains one element AND, if n is even, or one element OR, if n - odd, first input bus (2d-1) -th element And r-th rus (d p-2g + 2, r 2j-1, j 1, ") is connected with the output bus of the rth element is NOT, the input bus of which is connected to the first input bus of the 2d-th element And the speed of the first input bus (2v ± 1) -ro elements L And t-ro Rus (vn 2t + 2, t 2S. S - 1, -s-) connected to the input bus t-ro element NOT, the output bus of which is connected to the first input bus 2v-ro element OR t-ro rus, the second input bus of the first element I of the first rus is connected to the first modulus bus of the module, g- tuning bus of which (d 2, p) connected to the second input busbars 2 w-th and (2) -ro elements of the first rus (,), (n + 1) —the tuning bus is connected to the second input bus of the 2nd n-th element of the first rus, output buses of the first and second logical elements co-ro Russa (w 1, p-1) are connected respectively to the second and third input buses of the first logical element of the a + 1 th rus, the output bus (2p-lWp logic element (the th rus (-1, with 1, p-i) is connected to the second input bus 2 (p-1) -th and (2p- 1) of the logical elements (w + 1) of the rus, the third input buses of which are connected to the output bus of the 2 pth logical element of the wedge, advantageous buses (2n-2 w + 1) -th and 2 (n- ft) + 1Vro of logical elements a) of the Rus (# 17 | - /} are connected respectively with the second and third input buses 2Јncd) -ro of the logical element of the (Russ), output buses of the first and second logical elements of the nth rus are connected respectively to oh Khodnev and a second NAND gate buses (n + 1) st tier. 39 one J7 B YU five FIG. FIG. 6