SU1675853A1 - Device for automatic compensation for errors in measuring channel - Google Patents

Abstract

The invention relates to automation and measurement instrumentation and can be used to automatically compensate for errors in the measurement channel with periodic processing and outputting the measurement signal. The purpose of the invention is to improve the measurement accuracy. The device contains a sensor of the measured value, a switch, a signal splitter, two generators of exemplary signals, two subtractors, an encoder, a decoder, a comparator, a switch, a block for fixing the reference signal passing through the measuring channel. The principle of the device is to select the reference signal, the closest in size to the measured signal, transmit it through the measuring channel in a specially selected time interval, memorize the received signal in the fixing unit of the reference signal, select one of the exemplary signals of the second generator of exemplary signals, most close to the received one, subtracting its value stored in the block of fixation of the reference signal, and subtracting this difference from the value of the received signal from the sensor measured in antics. 10 il.

Description

The invention relates to automation and measurement instrumentation and can be used to automatically compensate for errors in the measurement channel with periodic processing and outputting the measurement signal.

The purpose of the invention is to improve the measurement accuracy.

FIG. 1 shows b, the lok scheme of the device; in fig. 2 is a block diagram of an encoder; FIG. 3 is a block diagram of a first switch; in fig. 4 is a block diagram of a second switch; in fig. 5 is a block diagram of a decoder; in fig. 6 is a block diagram of a switch; in fig. 7 is a block diagram of a first adder; in fig. 8 is a block diagram of a second adder; in fig. 9 is a diagram of the formation of the signal Y; on

FIG. 10 - time diagram of the device.

The device (Fig. 1) contains the measured value sensor 1, the first generator 2 exemplary signals, the encoder 3, the comparator 4, the switch 5, the measuring channel 6, the separator 7 signals, the decoder 8, the switch 9, the second generator 10 exemplary signals, block 11 fixing the reference signal transmitted through the measuring channel, the first subtractor 12, the second subtractor 13.

The encoder (Fig. 2) 3 consists of the first clock pulse generator 14, a group of n-1 first triggers 15i-15n-i with a counting input, a group of n first elements AND 16i-16n, the first element OR 17, and the corpse

01 00

ate

with

Dips from the first keys 18i-18n (the device for initial installation of the 15i-15n-i flip-flops is not shown).

Switch 5 (FIG. 3) consists of an inverter 19, a first 20 and a second 21 delay elements, a second 22 and a third 23 And elements, a second 24 and a third 25 keys, a second element OR 26.

The separator 7 signals (Fig. 4) consists of the first one-shot 27, the second trigger 28 with the counting input, the fourth key 29, the second block 30 of the initial installation.

The decoder 8 (FIG. 5) consists of a second clock pulse generator 31, an additional key 32, a pulse counter 33, a first memory register 34, a second 35 and a third 36 one-shot.

The switch 9 (Fig. 6) consists of a decoder-multiplexer 37 and a group of sixth keys 38i-38n.

The first subtractor 12 (FIG. 7) consists of a first subtracting unit 39 and a second memory register 40.

The second subtractor 13 (FIG. 8) consists of a third memory register 41 and a second subtractor 42.

The device works as follows.

The error compensation process is performed periodically. Moreover, the measurement period of the value of X | (period tf) alternates with an error release period (period TJI, where j corresponds to the magnitude of the signal YJ at the 1st time point).

During the measurement period ti, the value X) from sensor 1 goes through switch 5, separator 7 and measuring channel 6 to the first input of the second subtractor 13, acquiring the error of measuring channel 6 (Xi). Thus, the value Xi + AI is stored in memory register 41. At the same time, the value of X is fed to the first input of the comparator 4, where a sample signal YJI "X | (at the 1st moment of time, the signal is a j-ro level), which enters through the encoder 3 from the first generator 2.

Generator 2 generates n exemplary signals () that arrive

on the keys 18i-18n. Key 18 is triggered when a logical unit is created at the output of the corresponding element AND 16j. The duration Tj of switching on the jth key 18j depends on the period of arrival of the pulses g of the clock generator 14 and the sequence number of the reference signal YJ.

 G, npujfn;

Tj () g, Such an on-time and, therefore, the presence at the output of the encoder 3 of the signal of the level YJ is formed

a control circuit consisting of a trigger 15i with a counting input, triggered on the leading edge, and triggers 152 15p-1, triggered on the trailing edge of the pulse, elements AND 16i-16n. The duration of the signal Yn is increased by the time r due to the element OR 17.

The diagram explaining the operation of the encoder 3 is shown in FIG. 9, which shows the formation process at the exit.

a 4-step encoder (), each step of which has a certain value YJ and a duration Tj, i.e. pulse width modulation of the YI signal occurs. The steps have a backward discreteness in amplitude AY.

As a result of the operation of the encoder 3, the second input of the comparator 4 receives a step signal (FIG. 9) calibrated in amplitude and duration. Comparator 4

selects the reference signal stage closest to the one being measured, and at its output a control signal Z appears at the control input of the switch 5. Comparator 4 operates according to

next algorithm, 7 -

35

1. when Xi-Yj-0.5Ay 0; Oh, with Xi-Yj-0.5 Ay 0.

Thus, at Xi YJI, the comparator 4 generates a signal and the system goes from the measurement period to the allocation of the TJI error.

The signal through the inverter 19 and the element 22 turns off the key 24 and, with a time delay n formed by the delay element 21, switches on the key 25 through the element 23. As a result, the sensor 1 is turned off

from the OR element 26 and the measuring channel 26, and through the encoder 3 connects the reference signal YJI from the generator 2 exemplary signals,

The reverse transition from the TJI error selection period to the next measurement period ti-and occurs when the signal Z () changes, which leads to the disconnection of the third key 25 and the inclusion with the time delay TZ formed by the element

20 delays, key 24.

The time diagram of the system (Fig. 10) shows the Z pulses at the output of the comparator 4 and, therefore, the alternation diagram of the signals Xi and YJI

at the output of the measuring channel 6. The alternation of signals Xi and YJI occurs with the corresponding time delays 71 And T2.

During the TJI error isolation period, the pulse width modulated YJI signal through the first 5, second 7 switches and measuring channel b, acquiring the error Aji f (Yji), goes to the decoder 8, block 11 and to the subtractor 13.

At the moment the switch 5 is triggered, a temporary signal interruption occurs (a pulse of duration ri). This pulse, through the measuring channel 6, is fed to the one-shot 27 of the separator 7. The one-shot 27 outputs a pulse toggling the trigger 28 and, accordingly, the key 29. The trigger 28 is transferred to its initial state by block 30.

The signal (Yji + Ajf) from the second output of the separator 7 enters the block 11, the key 32 and the one-shot 35 and 36.

The one-shot 35 is triggered on the leading edge of the impulse, driving the counter 33 to its initial state. At the same time, the key 32 opens and transmits pulses from the generator 31 to the input of the counter 33. The pulse count continues until the signal ends (Yji + AJI), then the key 32 closes, the one-shot 36 triggered on the falling edge of the pulse, initiates the recording of information from the counter 33 into the register 34.

Block 11 stores the signal value (Yji + AJI) until the next signal Yi (l + 1) + Aj (i + 1) arrives. From the output of register 34, a signal characterizing the duration of a TJI is fed to a decoder-multiplexer 37, which connects one of the keys 38j. Thus, there is a selection signal YJI, coming from the generator 10 exemplary signals. Generators 2 and 10 exemplary signals must be configured so that the condition

Yi-Yj 5j Aj.

The signal YJ is fed to the first input of block 39, where the difference is determined (error of measuring channel 6)

(Aji + Yji) -Yj i AJ + 5j. which is stored in register 40.

This ends the period of the TJI error selection and the system proceeds to the next measurement period ti-n, during which the value (Xj + i + A1 + 1) is fed to the input of register 41.

In block 42, the error of the measuring channel b is compensated.

(Hn-1 + A i + i) - (Aji + dj) Xi + 1 + di - 5j.

Considering that AH-I-Ajr- (5i and are second order values of smallness compared with the error Ai d -dj, there is a significant improvement in measurement accuracy.

Claims (1)

Apparatus of the Invention A device for automatically compensating for errors in a measuring channel, comprising first and second subtractors, first and second generators of exemplary signals, and a sensor of the measured value, the output of the first subtractor is the output of the device, and its input of the subtracted is connected to the output of the second subtractor, that, in order to improve the measurement accuracy, and it introduced the block fixing the reference signal passed through the measuring channel, switch, comparator, switch, separator signal the encoder and decoder, the sensor input of the measured value is connected to the first information input of the switch and the first input of the comparator, the second input of which is connected to the second information input of the switch and the output of the encoder, the information inputs of which are connected to the outputs of the first the sample signal generator, the control input of the switch is connected to the comparator output, and the output of the device for connecting to the input of the measuring channel, the input of the signal splitter is the input of the device for connecting to the output of the measuring channel, the first output is connected to the input of the decremented second subtractor, the second output - with the input of the decoder and input block fixation of the reference signal passing through the measuring channel, the output of which is connected to the input of the second subtractor, the input of which is subtracted is connected to the output of the switch, informational inputs of which are connected to the outputs of the second generator of exemplary signals, and the address input with the output of the decoder, while the encoder contains a clock pulse generator, a group of n-1 flip-flops, a group of n elements AND, an OR element and a group of n keys whose information inputs are informational encoder inputs, outputs are connected, and are the output of the encoder, the control inputs of the keys of the groups from the first to (n-1) -th connected to the outputs, respectively, of the elements AND groups from the first to (n-1) -th, whose inputs are connected to the inverse outputs of the groups triggers, direct output of each trigger group, except (the nth is connected to the counting input of the subsequent trigger group, the counting input of the first trigger of the group is connected to the forward output of the clock generator and the nth input of the nth element of group I, the inverse output of the generator clock pulses are connected to the n-th input of the first element AND of the group, the first and second inputs and output of the OR element are connected respectively with the direct output of the (n-1) -th trigger, the output of the n-th element of the AND group and the control input n- go key group. Fi1 R one SJQirj RZG) I  1 & 11 to I W Qi: J I at Ug ". # FIG. 2 &, - $ V. R one ) jg / rj I n Qi J -v from 2 Mind nago channel FIG. five 3 g it chg fat + t) fT LK F “g. 9 i Outputs Vlakob V 4 /