SU1672528A1 - Memory element - Google Patents

Abstract

The invention relates to electronic computing, in particular, to trigger memory elements for computer memory devices. The aim of the invention is to increase the reliability of the memory element. The goal is achieved due to the fact that the second terminals of the first and second resistors are connected to the collectors of the first and second transistors, respectively, the first emitters of which are connected to the second output of the primary and the first output of the transformer secondary windings, and the second emitters are connected to the first and second discharge buses, respectively The second terminal of the secondary winding of the transformer is connected to the first terminal of the primary winding of the transformer. 1 il.

Description

The invention relates to electronic computing, in particular to trigger ’memory elements for computer memory devices.

The aim of the invention is to increase the reliability of a memory element.

The drawing shows a schematic diagram of a memory element.

It contains a first resistor 1, a second resistor 2, a first transistor 3. a second transistor 4, a first bit line 5, a second bit line 6, address line 7. transformer 8.

The memory element works as follows. 1

This element can be in the following modes: storage of information when the power is on; selected state (and reading); record; storage of information when the power is off. 2

In the information storage mode when the power is on, information is recorded in the transformer 8 on a ferrite plate. In this mode, if O is written in the trigger, the emitter current of the open 2 transistor 3 is shorted to ground via bus 7. This current. flowing along the conductor that connects the first emitter of the open transistor 3 to the bus 7, creates an electric field 2 around the conductor, the voltage of which must be equal to or greater than the saturation field of the ferrite plate of transformer 8 and magnetize it to a saturated state. If in trigger 2 the information after recording changes, transistor 4 opens and due to the fact that the conductors connecting the first emitters and bus 7 are connected in the opposite direction, the current of transistor 4 flowing through the secondary winding of transformer 8 will have the opposite direction with respect to the current the first transistor 3, respectively, the electric field created by it will be opposite to the field of the first trans-

the resistor 1, and the transformer 8 is magnetized to the opposite saturated state.

When the power is turned off, information about the trigger state will be stored in the transformer 8. At the time of connecting the power to the winding of the transformer 8, the induction emf acts due to the residual magnetization of the plate. In a winding in which the magnetic field is opposite to the magnetic field of the ferrite plate, the induction EMF induced in it will be negative; in the other winding, the magnetic field will be aligned with the magnetic field of the ferrite plate and the induction EMF induced in it will be positive. With other trigger parameters equal, the first to open is the transistor 3 or 4, which will have more base current, i.e., for which the induction emf is positive.

Claims (1)

Claim A memory element containing two transistors, two resistors, a transformer, the first terminal of the primary winding of which is connected to the address bus of the memory element, to the power bus of which the first conclusions of the first and second resistors are connected, the second conclusions of which are connected to the bases of the second and first transistors, respectively, characterized in that, in order to increase the reliability of the memory element, the second conclusions of the first and second resistors are connected to the collectors of the first and second transistors, respectively. the first emitters of which are connected to the second terminal of the primary and the first terminal of the secondary windings of the transformer, respectively, and the second emitters are connected to the first and second bit buses of the memory element, respectively, the second terminal of the secondary winding of the transformer is connected to the first terminal of the primary winding of the transformer.