SU1672454A1 - Large-scale integrated circuit checker - Google Patents

Abstract

The invention relates to digital computing, in particular, devices for testing large integrated circuits (LSIs), and can be used for test monitoring LSI microprocessor sets. The aim of the invention is to increase the completeness of the control. For this purpose, a device that generates initial addresses, an exchange control unit, and a test generator are entered into the device containing the reference block, the clock pulse generator, the comparison block, the display register, the master oscillator, the mode setting block and the bus driver block. 2 hp f-ly, 8 ill., 1 tab.

Description

ate with

The invention relates to digital computing, in particular, devices for testing large integrated circuits (LSIs), and can be used for testing the LSI microprocessor sets.

The aim of the invention is to increase the completeness of the control.

Fig „1 shows the structural scheme of the proposed device; Fig. 2 is a block diagram for setting modes; in FIGURE 3, a block diagram of the formation of initial addresses; in fig. 4 is a diagram of an exchange control unit; figure 5 - diagram of the test generator; Fig. 6 is a block comparison diagram; 7 is a diagram of the register display; on Fig - timing charts of the device.

A device for controlling large integrated circuits (FIG. 1) contains

the mode setting unit 1, the initial address generation unit, the master oscillator 3, the exchange control block 4, the clock generator 5, the test generator 6, the bus driver unit 7, the control object 8, the reference block 9, the comparison block 10, the display register 11 and has input 12 start, input 13 cycle, input J4 stop, input 15 modification of the program control. The control object 8 (verifiable large integrated circuit) is not directly included in the device and is used only to clarify the principle of its operation,

The mode setting unit 1 is designed to generate control signals that initiate and terminate the monitoring process. The block 1 setting modes (figure 2) contains the element

05 1

.Јъ SP

Dh

And 16, the element OR 17 and the trigger 18 start.

Fig. 3 shows an example of the implementation of block 2 of forming initial addresses in relation to testing an LSI of a microprocessor KP 580 IR 80 Block 2 contains the first 19 and second 20 formers of a single pulse, a stake converter 21, the AND 22 element and the OR 23 element.

The shaper 19 is designed to produce a negative pulse at its output with a pulse that works; when the control signal at the input of the shaper changes from 0 to 1, the pulse duration is determined by the number of ticks needed to set the object 8 of the control and the block 9 to its initial state. ie (for BIS KR 580 IK 80 not less than cycles). A negative impulse from the output of the foror of the rotator 19, arriving at the input of the resolution of the converter 21 of codes and to the first input of the element 22, logically turns off the block 2 forming initial addresses from block 9 for the time required to set block 9 to its initial state.

The shaper 20 is designed to generate a positive pulse at its output, the duration of which coincides with the duration of the SYNC signal at the microprocessor control output of the KR 580 IR Ya0 Impulse is generated when the input signal of the driver in O is changed.

The converter Kodoz 21 is designed to convert a word — the state of the BIS microprocessor to the starting address of the program that implements the exchange protocol corresponding to the given state word. The code converter 21 is a combinator circuit implementing the following functions. Microprocessor KP 580 IK 80 has 10 machine cycles. Each cycle has its own protocol (algorithm) of exchange with each exchange protocol implemented by the corresponding program from exchange control unit D

The initial address of a specific exchange program is formed at the output of the converter 21 codes, depending on the block 9 state word (input D2) from the code at input 15 of the program modification 0

0

five

0

five

0

five

0

control frame (input D1) and the value of the signal at the output of the resolution Y.

Denote by A, A ,. “. , A (, the initial addresses of the corresponding exchange programs, which ensure the implementation of the exchange protocols under the condition (that the speed of the BIS microprocessor and the speed of external ones with respect to the BIS device coincide. - For example, A.) - the starting address of the program corresponding to the machine cycle Ml , A ,; the initial address of the program, the corresponding reading cycle from the memory, and m, p, and Ac denote the initial address of the installation program for the object 8 control and block 9 to the required state, A, ..., denote the initial addresses of the corresponding programs bman, providing the implementation of exchange protocols, provided that the speed of a certain possible external device BIS microprocessor is lower (for example, the recording in the memory is equal to two LIS clock cycles) .A, .O., A) O denote the initial addresses of the programs that ensure implementation of exchange protocols with other time parameters of external devices (for example, the cycle of accessing the stack in duration is equal to It to the clock clock of the LSI) 1 1 p.

You t) a specific group of programs

(JSC, A /,.,), (A, A ;, .., A; O),

(A, A (,, o, AJ0), „„ „is performed with the help of codes on inputs D1 of the transducer n 21„

The program group number is determined by the number of k possible combinations of the time parameters of the external devices of the BIS microprocessor, at which it is necessary to ensure the verification of the control object. Then the truth table of the combinational circuit - converter 21 has the form (X is an indifferent signal value) presented in the table.

In particular, the converter 21 can be implemented as a programmable logic matrix КР 556 РТ1 (16 input, 8 output signals) or in the form of a ROM (КР 556 РТб or К РТ2), etc.

The master oscillator 3 is designed to generate pulses that synchronize the operation of the device. The pulses at the output of the generator 3 are generated under the condition that on its control 1

the input is supported by the signal l. . units

The exchange control unit C is designed to generate input control signals of block 9 and an object, control, generator control signals 6 tests, control block 7 bus drivers and control of display register 11. The exchange control block k (Fig.) Contains the first 2, second 25, third 26 and fourth 27 elements AND, delay element 28, counter 29, memory block 30 and has outputs of control field 30.1, control field of bus driver unit 30.2, poll field Test Generators 30.3 and Comparison Resolution Floor Z0. „

The memory block 30 is designed to store programs that control the exchange with the block E and the control object 8, as well as the generator 6 tests, the block 7 bus drivers and the comparison block 10 Depending on the particular application of the device, the memory block 30 can be made Permanently ioi about either operational memory jjii i.

Shaper 5 TLMOOYU them. It is designed to form a series of springs supplied to the input of the object 8 of the control unit 5klo 5. For example, for the BIS microrog / CCCOPJ KR 580 IR 80, two - and one sync pulses - F1 and F2 are used.

Generator 6 tests prednnz (en for generating commands, addresses and data supplied to the bidirectional outputs of the object 8 control and block 9. The generator 6 tests (figure 5) contains the delay element 31, the counter 32 tests, block 33 PLI ty tests, The register is 3k and has outputs 3.1 floor tests and output 3.2 half the end of the gost.

Comparison unit 10 is designed to compare the responses of object 8 of control and block 9 at times determined by a signal at its control input. Comparison unit 10 contains (FIG. 6) the first 35, second 36 and third 37 comparison circuits, the AND element 38 and the result trigger 39,

The display register 11 is designed to display the result of the BISO control. The display register 11 (FIG. 7) contains the element NOT 0, the first k and the second k2 triggers, the element 3 indie

0

five

0

five

0

five

0

five

  ods-n and we-jHi i in, ;; - cl and u Not fit.

Nd oig, 8 the following notation is used: i-1 ,, o,, 1 $ - the first, second, and so on clock pulses; , T2 - synchronization at the outputs of a formi tel 5 clock pulses; RESfvT is a signal at one of the outputs of a group of outputs 30.1 of the field supplied to the control input of the installation of object 8 of the control and block 9 to the initial state; SYNC is a signal on the bypass of block 9, indicating that the bi-directional pins are yc. there is a BIS microprocessor state word; A0 - the starting address of the installation program of the object 8 control and bl-jx ,. 9 to the initial state; A, (- NL1 -,. Mi - 0,; (program cycle of cycle M1; / - delay value of the delay element 2k. The numbers for temporary dis: grams from r. 8 indicate the elements whose output signals are shown in diagrams.

The device works as follows.

Group start work in a block of 30 liters. Hello, management programs. In the zero word of the block l n is about the discharge, so k. output ZC.2, value 1 is written

Nchkn, -, from address A, is located npt r.zmma installation object 8 control and block 9 to its original state, with LDRS. A, is the program of the first igomentomento (for example, for BIS KR YAO IR 80 - issuing program control signals of the Ml cycle signal), from the address AV, the program of the second exchange protocol (for example, the program for issuing control signals during the memory access cycle), etc. Moreover, each clock of the generator 3 corresponds to one word of the memory block 3. In each. The following information is recorded in the word. In the bits corresponding to you; Ode 30.1, the values of the input, - | - - x control signals of object Cyntrol 8 and block 9 on the considered clock are recorded. In the discharge corresponding to the output 30.2, the value determining the direction of information transfer through the block 7 at the considered clock, 3 bits corresponding to the output 30.3, is recorded, the value 1 is recorded if at the considered clock from the generator 6 output to bidirectional

The outputs of the object 8 of the control and the block 9 are submitted to the test (and, in the opposite case). In the bit corresponding to the output 30 ,, it is recorded 1 if the responses of object 8 and block 9 are compared (and O otherwise) at the considered cycle. The number of words of each program is determined by the number of ticks needed to implement the corresponding exchange protocol. For example, for BIS KR 580 IR 80, each machine cycle includes up to five cycles.

Similarly, starting with addresses

A / A, ... And us, the second is loaded from .and

addresses g, 0,

A o.AV.ocjA - third group of programs, exchange management, etc.

Block 33 is loaded with ghodnye effects, tse. codes, addresses and data supplied to the control unit 8 and block 9 at the instants of time determined by the arrival of the interrogation signal at the control input of the 6 test generator. In the initial state, the trigger 18 is set to O, the counters 29 and 32 have zeros written in, the result trigger 39 is set to 1, the triggers 41 and h2 are set to E P (conditionally not shown in Fig. 1-7). When this generator 3 is turned off, the contents of the zero words are set at the outputs of the memory unit 30 and the test memory unit 33. Moreover, since the zero word bit corresponding to the 30 ° 2 output (Fig. 1) is set to D, unit 7 is configured to receive information from the bidirectional outputs of the control object P and the block 9. Thus, the influence of the output of the test generator 6 on the Bidirectional outputs prior to installation of the object 8 of the control and of the block 9 to the initial state.

Suppose that at the input 15 of the modification of the control program a zero code is set. When a start signal is applied to the input 12 of the device, trigger 18 (figure 2) is set to state 1. Signal 1 from the output of trigger 18 is fed to the inputs of the formers 19 and 20 (FIG. 3). At the same time, the considered signal from the direct output of the trigger 18 for start-up is fed to the input of the generator 3. A single pulse shaper 19 (FIG. 3) produces a negative pulse of duration (in the case of LSI

0

0

five

0

five

0

five

KP 580 IR 80) k tact. Shaper

A 20-pulse produces a single pulse (Fig. 8) with a duration of no more than one cycle. At the same time, generator 3 starts generating a continuous sequence of pulses, and driver 5 produces synchronization 1 and 92, which are fed to the inputs of control object 8 and block 9. to the input of the resolution V of the converter 21. Since V O and D1 0, on the output code of the converter

21 the AO code is set - the address of the initial word of the installation program of the control object 8 and the block 9 to the initial state. At the same time, the considered pulse sets the output of the element 22. Thus, the control outputs and the bidirectional outputs of block 9 are logically disconnected from the outputs of the initial address formation block 2 at the time of installation of the control object ft and block 9

in the initial state.

A pulse from the output of the imaging unit 20, through element 23, buys into the start input of the program of the block b (Fig.). A0 values. This starts the process of reading the memory block 30 and the values of the corresponding bits of the first word of the program appear at its outputs 30.1-30.4. The signals from outputs 30 o 1 are fed directly to the control inputs of object 8 of the control and block 9. In the case of LSI KR 580 IR 80, the input control signals are zero, with the exception of the RESET signal — resetting the output state corresponding to output 30.2, set to 1 — reading from the bidirectional outputs of the object 8 of the control and block 9. The bits corresponding to the outputs 30.3 and 30.4 are also set to 0m, i.e. Interrogation of the generator 6 tests and comparison of the responses of the object 8 of the control and the block 9 are not performed,

By the time the master oscillator 3 generates the second clock pulse, the output of the driver 20 is set to O (Fig. 8), therefore, the output of the element 23 is set to

value О The second clock pulse Ґj from the output of the generator 3 through the element 2G is fed to the input +1 of the counter 29 and its content becomes A o + 1. From the blocks, 1 the next word is read. In t BIS KR 580 IR 80, the considered -f - in coincides with the first, i.e. on the left input RESfT and in the second stage the value 1 is applied

Similarly, with the arrival of the third m of the pulse, the contents of the account of peak 29 become 0 + 2 and the next word is read in memory block 30, which also supports the value 1 at the RISE1 control input.

With the arrival of the fourth clock pulse c, the contents of counter 29 become equal to A0 + 3 (Fig. 8), the next word is read from memory block 30, which sets the RESET signal to O. At this point, block 9 is reset and at its output the value of O is set. However, at the output of the forms i 1, it is negative because of them, and the value of

 iP, the operation of the device tg (3t, ifc) () tc with the signals at the inputs of the unit and P, the word of state.

By the arrival of the fifth and r source pulses t (, and tf sig-Y - h N m - the outputs of block 9 are equal to O, the po r g outputs of the elements 22 v 23 are set –themes in O, the clock pulses go to the +1 of the counter 29 which sequentially generates the addresses AO + k and AQ + 5. The memory memories read from the block 30 do not change the signals on the control signals of the control object 8 and 9. Thus, the HIM oid or control signals g of the block outputs are provided 9.

6, the time interval between the sixth and seventh clock pulses and the OG, block 9 sets the sig-ian SYNC to 1, indicating that the word BIS of the microprocessor, block 9, is outputted from the bidirectional outputs value 1, which through element 23 (FIG. 3) enters the program start input. At the same time, the state of the LSI is still being received at the information input.

0

five

i j

0

five

0

five

 -1,1If 1 L T, g I

The value of 1 arrives at the input of the resolution of the prelag 2I from the generator 19, the output of the iv-v of the consumer 21 is set to A, the exchange program corresponding to the word of the state at the input D2 of the tvtDuser. In the case of BIS KR 58 and O at the time of pre-razsuzsvatel 2 | G, C1 is the word of the state of the cycle M1 of the fi from the cho command, mnt of its output, the code L is initial, i; -) - g, the exchange programs are considered, and the j is

Ged my clock pulse L / through 2 i i is tight and the synchronous input counters 29 ig.) J describes the address A in it (4, t iy t it. Reading process from the block jT n gi, -gr of which in; / 1 ° ts g htc zmma os-menr, 4n cycle 1 .i about the situation of the people of 301 -tciynaioi

UPR RJ YUSHCHI Z / CDi1 cf KOCH, 8 AND I fk u t q, fi.lXO 30 - r f / iOK 7,

from the out; / 1 p jp.i and - - the first highways - fj ijit-M ° 4T about 6 h 7 i tnettRCHHO. / ° m, urr rprchd, with i E e gsvup1TS F Pt.1DU 3G. ,) Members EJ P | „G1J pV h Ha B (CMi / TdhTOriblu

im y, v v. output f (l 1l meme 28 (fgg.)

LK P o -if t-77) C7} pa t t Not INPUT

Rl, w isnie (re | zmegi g1 lokgE 1 fi. When oiCf P trigger .j | (. T. HagyyG - to kn r.Lo iT GROVN nor .KOV

ebge-i o r ntrom) - and Spock, having produced f-b and lem M ijM3. n, j. je g ipn-1D n g ngchkoz in toigg - pt 3 J, c 3yribT i g j, drncb 44. is initial, - i1, in case of s) the case of the values (AT C7K1ICHOP SOSTO tmggers 7b results did not change, and print it on the day - 1st liar from the memory T memory, tr (idle)

By the time of / ode. on the eighth tokens; one block removes the 3VNC signal, the poet, the output ele; Enpv 22 l 23 sets & gzny in O and -j time cycles. 1 pulse impulse through 25 is fed to the input +1 of the counter 29 and its contents become different At + 1. With JTOM, the second word of the loop program is read from memory block 30 Ml and the control inputs of the object 8 and block 9 are given corresponding signals. If oazr d, corresponding to output 30.3, ycTinoBjien to 1, after time f clockwise

from the output of the element 28 through the element 26 is fed to the input of the survey generator

6 tests. In this case, in register 3 (FIG. 5), the zero word is recorded from the output of test memory block 33, the corresponding bits of which are output from the outputs to the input of the block

7 and then the control object 8 and the block 9. At the same time, the pulse from the polling input through element 31 enters the +1 input of the test counter, increasing its content by 1. This starts the reading process from the test memory block 33 and sets the content of the next word at its output. Thus, by the arrival of the next interrogation signal, the next test „

The next pulse of the generator 3 again increases the contents of the counter 29, which becomes equal to A + 2 and so on until

ten

20

Yes, the element 0, and in the trigger 2 - the value of 1 V At the same time, the AD element of the indication is turned off. But this control process is completed.

Case 2. When polling test generator C, register 3 (FIG. 5) writes a code that sets output 3.2 of test to I. A value of 1 from the output resets the counter of 32 tests to zero, preparing it for re-writing the memory addresses in memory 33. When.-Gom on the moves of the memory block 33 by pl;: here is the contents of the zero word. At the same time, the value 1 from the output of the end of the test enters the second rcode of the element 16 of block 1 (FIG. 2).

If the input of the device's cycle 13 is set to 1 (single test run mode), the output of element 16 is set to 1 and trigger element 18 is reset via element 17.

the execution of the cycle Ml is not completed. generator 3 and driver 5. Value of 1 with inverse output trigger 30

The start 18 is fed to the synchronization input of register 11 and writes the result of the control to the triggers 1 and 2 — the value 1 to the trigger k and the value O B of the player 2. This turns on the element 3 of the display Glad. This process is complete.

Its: and from the input 13 of the cycle of the device, the value O is applied (the multiple block mode 9 again sets the state word and sets the SYNC signal to. At the same time, block 2 again forms the initial address of the corresponding exchange program and outputs the program start signal. By setting the corresponding word bits memory 30 in O or 1 provides control signals to the object 8 and block 9, control block 7, interrogate the test generator 6, and test run), the output element of the solution of the comparison block 10, .16 remains in the mule regardless of sign The following cases, the 18 start-up does not change its state. The monitoring process continues, and with the arrival of the next polling signal of the test generator 6 (Fig. 5) to register 3 from the output of the memory block 33 tests written zero word. The corresponding bit from the output removes the reset signal of the counter 32, and the interrogation signal through

Case 1: When doing a comparison

A discrepancy between object 8 and block 9 is detected. "At least one of the circuits 35 -.37 (Fig. 6) produces at its output a value O, which is recorded through element 38, if the comparison is allowed in this cycle, in result trigger 39 The value 1 with the inverse output of the flip-flop 39 enters the input of the result of the block 1 and, through element 17 (Fig 2), resets the trigger 18 for the start signal to the Signal signal. direct gain trigger trigger 18 blocks the operation of the generator 3 and the driver 5

40

45

50

the delay specified by element 31 increases the contents of counter 32 by one, etc.

In the mode of multiple sweep tests, the monitoring process can be terminated by supplying the value of the device to the device stop input. At that, s | - 0 1 through element 17 (Fig. 2)

In the mode of multiple sweep tests, the monitoring process can be terminated by supplying the value of the device to the device stop input. At that, s | - 0 1 through element 17 (Fig. 2)

ceases to produce sync serials. Whitefish-...

cash 1 with inverse trigger output - resets trigger 18 into O,

18 start-up is fed to the synchronous input, while the operation of the generator 3 and the formation of the register 11 (php, 7) and the recorder-rozatel 5 is blocked, and in the register

em in the trigger. And the value of O from output 11 is similar to that described above.

0

Yes, the element 0, and in the trigger 2 - the value of 1 V At the same time, the AD element of the indication is turned off. But this control process is completed.

Case 2. When polling test generator C, register 3 (FIG. 5) writes a code that sets output 3.2 of test to I. A value of 1 from the output resets the counter of 32 tests to zero, preparing it for re-writing the memory addresses in memory 33. When.-Gom on the moves of the memory block 33 by pl;: here is the contents of the zero word. At the same time, the value 1 from the output of the end of the test enters the second rcode of the element 16 of block 1 (FIG. 2).

If the input of the device's cycle 13 is set to 1 (single test run mode), the output of element 16 is set to 1 and trigger element 18 is reset via element 17.

The start 18 is fed to the synchronization input of register 11 and writes the result of the control to the triggers 1 and 2 — the value 1 to the trigger k and the value O B of the player 2. This turns on the element 3 of the display Glad. This process is complete.

Its: and from the input 13 of the cycle of the device, the value O is applied (multiple test run mode), the output of element 16 remains in the mule regardless of the sign

45

50

the delay specified by element 31 increases the contents of counter 32 by one, etc.

In the mode of multiple sweep tests, the monitoring process can be terminated by supplying the value of the device to the device stop input. At that, s | - 0 1 through element 17 (Fig. 2)

...

- resets trigger 18 to O,

11 is similar to the one described above.

the result of the control, and the switch and ment 3 of the indication 1den.

Verification of the control object pt of other combinations of temporary parameters of the exchange protocols performs and / sets Hi input 15 modifications and control programs the codt (number) of the corresponding group (Ј о,,..., Rtjv ij the initial addresses of exchange control programs. The specified code is received informational Inputs 1) 1 of the converters 21, therefore, after starting up in the IP process of forming the initial address of the exchange programs, the output addresses of the converter 2} generate the start addresses, A ,, A, and so on, and the device operates as described.

well

Claims (3)

1. Device for large-scale integrated circuits, containing a reference block, a clock pulse shaper, a comparison block, an indication register, a master oscillator, mode settings and a blog, and 4 alternators, and the trigger mode settings the secretary general in the dictation unit MI. n, is keyed to sync input 1gt-mr | s, indications, output is connected to the sync input and pnc gc clock pulses, output kg is connected to this sync input and g i block and is the output of devices rm to connect to the sync input 1 i control, the first information input / output of the bus driver unit is the input of the device for connecting to the terminal 4, the driver and the controller, and the ecog 1 INFORMATION Pg About JJHH shaper is connected to the information INPUT-VYHG qe i f POG NOGO block, the first information output of the block of bus Formitv ttels - ps dk yuch6N To Perroko INFSOMACI) NNOMU iqy the comparison unit, the second informait, and the JH- output output of the bus for the transmission line) are connected to the second IMI house of the reference unit, and t (the memory input of the CPTR unit of the R & D workstation under the information output / i kt kontrol, information vyhg- (eg the nth block is connected to five O j five i (mc cn fn input; reference comparison, ip code 1– 1 input block input i pass- Hi ning is the input of the device for reading the sign of the control object, the output recognizes the tone of the reference block of the pin with the sixth information The Comparison Glockch input, the output of which is connected to the information input of the indication display, the start, cycle / p stop inputs of the device are connected to the rrt corresponding inputs of the set-HI mode, which is opposite, U7o. r ,, i, it contains a block of form- "and h of the addresses, block to control the ogmen of the generator v tests, and p ix l i-a and the installation of the unit sets the clamp is connected to the input of the head of the vcTdHoekn block of the block forming the one of the addresses, the result TL, block the formation of the initial address (. i with the start input programs of the exchange control, the information output of the formation unit of the rv whose addresses are connected to the input if it is neHMq, the keys w - opoio are connected to the input terminal, the second ь - BL KR upvpvl (no trader (ohm podku to YuChRg control, to him the input block -nn / vin emirotate, third output (h (/ prtvpeni exchange connected with o i p i sp-sheni comparison unit, four hours in one unit ypapvg n exchange- i m g dk to er to ix l, U mode coupon G (L C R I) TAPE TJA 9 DEVICE INPUT It is located in the mode Control Object, the information output / output of the unit is connected with the first and information input of the block. Formation of initial addresses, the output of the reference block is connected to the resolution input of the Formation of initial addresses unit, the comparison output is connected with By the progress of the result of the re- and 1mm task block, the output of the end of the stop generator test is connected to the input of the end of the test, the Ti of the lacquer setting, the clock generator of the tests is connected to the information input of the bus farmer unit; gene- present rzgort RHGDU connected to exchange synchronization control unit, the input m; of the device control program specification is connected with the second information. Lb16 the input of the unit forming the initial addresses with 2C The device of claim 1, wherein the exchange control unit comprises four AND elements, a delay element, a counter and a memory block, the first input of the first AND element connected to the inverse input of the second AND element and a program start input block, the information input of the counter is the input of the operation of the block, the input of the delay element is connected to the second input of the first element And the second input of the second element And is the synchronization input of the block, the output of the first element And is connected to the input of the counter, the output of the second element I is connected to the counter input of the counter, the output of which is connected to the address input of the memory block, the output of the delay element is connected to the second input of the third element AND and the second input of the fourth element AND, the outputs of the control field of the memory block form the fourth output of the block the control field of the block of bus drivers of the memory block forms the second output of the block, the output 0 five The polling field of the test generator is connected to the first input of the third element AND, the output of which is the first input of the third element AND, the output of which is the first trick (so far, the output of the comparison field of the comparison memory block is connected to the first input of the fourth element AND, whose output is third output block with 3. The device according to claim. Characterized in that the test generator contains a.-Vortika element, a test counter, a memory block, a test, and a register, with the input of the delay element connected to the synchronous input of the register and the input of the generator poll, the output of the delay element connected to the estimated input of the test counter, the output of which is connected to the address input of the test memory block, the output of which is connected to the information input of the register, the outputs of the test field of which form the clock output of the generator, the output floor of the register’s test end is connected to the input of throwing the meter of tests and is the output of the end of the test gecheG | TORL " but t Gff Ј-gpf 02, and | 2 % 51 SH dsch 7 77 / 9L g I dgpf 7/41 FIG. eight