SU1670771A1 - Controlled pulse generator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in various devices with electronic frequency tuning. The purpose of the invention is to improve the accuracy and expand the scope by providing additional possibilities of frequency control - by introducing two elements OR-NOT 3 and 4, a dual electronic switch 5 (5 - 1 and 5 - 2), the second transistor 7. The generator also contains two Inventor 1 and 2, current source transistor 6, inverters 1, 2, resistors 8, 9, capacitors 14, 15 and resistors 10, 11, 12, 13. 2 Il.

Description

ABOUT

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figure 1

The invention relates to a pulse technique and can be used in various devices: electronic frequency tuning, for example, phase locked loop devices.

The aim of the invention is to improve the accuracy and the expansion of the field of application by providing additional possibilities of frequency control.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - time diagrams that show his work.

The controlled pulse generator (Fig. 1) contains two inverters 1 and 2, two two-input elements OR-NE 3 and 4, a dual electronic switch 5 (5-1 and 5-2) transistor 6 of the current source, field-effect transistor 7, Inverters 1 and 2 are covered by feedback each through a switch 5-1 and 5-2 and resistors 8 and 9, respectively.

The outputs of inverters 1 and 2 are connected to the first inputs of the elements OR-NE 3 and 4, respectively, through voltage dividers on resistors 10, 11 and 12, 13, respectively. The outputs of both elements OR 3 and 4 through time, the driving capacitors 14 and 15 are connected to the inputs of inverters 1 and 2. The output of the element OR NOT 3 is connected to the free input of the element OR NOT 4, and the output of the element OR NOT 4 is connected to the free input of the element OR NOT 3.

The collector of the transistor b is connected via an electronic switch key 5 to the inputs of inverters I and 2. The control input of the switch 5 is connected to the output of the OR-NO 4 element, which is the main output of the entire controlled pulse generator. The first input of the generator is connected to the base of the transistor 6. The second input of the generator is connected to the gate of the field-effect transistor 7, the source of which is grounded, and the drain is connected to the emitter of the transistor 6.

The third input is an auxiliary input and serves to connect an external resistor (external resistors) to the generator instead of the field-effect transistor 7. In this case, the generator will be controlled by the voltage applied to the first input and the resistance connected between the third input and the common wire. In this case, the field-effect transistor 7 should be closed with the corresponding voltage to the second input, or not installed.

The outputs of the inverters 1 and 2 through the resistors 8 and 9, respectively, are connected to the contacts 16-1 and 17-1 of the keys 5-1 and 5-2. The select contacts of the keys are connected to the inputs of inverters 1 and 2.

The controlled pulse generator operates as follows.

When the voltage at the output of the element OR NOT 4 corresponds to 1 (see the temporary

the operation diagram of FIG. 2), the selector contact of the key 5-1 is connected to the contact 16-1, the selector contact of the key 5-2 is connected to the contact 17-2 and vice versa, when the voltage at the output of the OR-NOT 4 element corresponds to 0, the selector contact of the key 5- 1 is connected to pin 16-2, the select key pin 5-2 is connected to pin 17-1.

At the time of occurrence of 1 at the output of the generator 5, the output of the element OR-HE 4 (time ti) and at the point Cz in the timing diagram of FIG. 2) a current source is connected to the input of the inverter 2, the transistor 6 and the voltage at its input starts to fall linearly with a speed proportional to the current source current (point D2) of the timing diagram immediately after ti). At the same time, a negative differential is transmitted through the capacitor 14 to the DI point from the output of the OR-NOT 3 element and the capacitor 14 begins to charge through the resistor 8 to the voltage at the point AI. After some time (at the instant in the time diagram of FIG. 2), the capacitor 14 is charged to the extent that

0 that the voltage at point A1 falls to a level at which inverter 1 enters active amplification mode due to feedback from the output of inverter 1 to its input (from point AI to point DI) through resistor 8. Such

5, the inverter status may continue for as long as desired. In this case, the voltage at the point Bi will be set such that the element OR NOT 3 perceives its level as zero. However, due to the presence of the unity level at the second input of this element, no switching in the circuit occurs at this moment.

When the voltage level is at point D2, due to the discharge of the capacitor 15 by the current

5 source, reaches a level at which the output of inverter 2 (point A2) has a voltage close to 1 (time to on the timing diagram), the voltage at point B2 becomes such that the two-input element

0 OR-NOT 4 will take it as 1, then at its output by Wits 0. And since at the second input of the element OR-NOT 3, there was already zero, then at its output by Wits 1. Key 5 switches, after which the capacitor 15

5 will be charged to the level of the output voltage of inverter 2 (point A2), the capacitor 14 will be discharged by the current source of the transistor 6 to the switching level of the inverter 1. At the moment inverter 2 will become in pc. the autostabilization of the output voltage and thus a decrease in the voltage at points A2 and Va will not prevent at the moment ts from making the next switching of the generator circuit to the production of the next period ..

The time of the next switching is determined by the magnitude of the current of the transistor 6. hence the voltage at the base and the resistance value in the emitter circuit, which changes with a change in voltage across the solution of the field-effect transistor 7.

The elements of the generator are made on the 561 series of microcircuits or another series built using K-MOS technology.

Thus, in comparison with the prototype, the proposed generator has wider functionality due to the presence of two control inputs and greater accuracy of voltage-to-frequency conversion, since the control voltage affects the processes of discharge of the generator capacities continuously.

Claims (1)

Invention Formula A controlled pulse generator containing the first and second inverters, the first and second capacitors, the control bus, the first transistor, resistors, characterized in that, in order to improve the accuracy and expand the application area by providing additional frequency control capabilities, it introduced two two-input elements OR NOT, a dual electronic key, a second transistor, two control buses, the output of the first inverter through a resistor connected to the first input of the first key, the output of the second inverter through a cut The transmitter is connected to the first input of the second switch, the collector of the first transistor connected to the left bus of the control voltage is connected to the second input of both keys, the emitter of the first transistor is connected to the third bus of the control voltage and the drain of the second transistor, the source of which is connected to the common the bus, the gate is connected to the second bus of the control voltage, the output of the second logical element OR NOT is connected to the output bus of the device and to the control inputs of the first and second keys, as well as to one of the inputs of the first OR NO, the output of the second OR OR is connected through time setting the capacitor to the input of the second inverter and to the output of the second switch, the output of the second inverter through a voltage divider on the resistors is connected to the first input of the second two-input element OR NOT , the output of the first logical element OR is NOT connected to the second input of the second element OR NOT and through time sets the capacitor to the input of the first inverter and to the output of the first switch, the output of the first inverter through a voltage divider pax connected to the second input of the first logical element OR NOT. FI.2.