JPS6349404B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an oscillation circuit, and particularly to a circuit using a piezoelectric vibrator such as a crystal.

Conventionally, in addition to the one-stage CMOS inverter type shown in Figure 1, the three-stage CMOS inverter type shown in Figure 2 has been used as a crystal oscillator circuit for electronic watches with a relatively low frequency such as 32KHz. There is something. The one-stage CMOS inverter starts oscillating stably, but the gain of the feedback loop of the oscillation circuit is not sufficient, and the rise and fall of the oscillation waveform are not steep.
A shortcoming is that a through current flows through the inverter directly from the power supply to the ground, resulting in high power consumption. In the case of a device using a three-stage CMOS inverter, the gain of the feedback loop is high, so the rise and fall of the oscillation waveform are steep, close to a square wave, and the through current is extremely small. Therefore, the current consumption during stable oscillation is low. However, since the gain of the feedback loop is high, the crystal oscillator X ₂ acts as a capacitor with the capacitance between its terminals, forming an unstable multivibrator. In such a state, oscillation will start at a frequency higher than the resonant frequency of crystal resonator X ₂ , for example 80KHz, and it will not be possible to shift to oscillation at the resonant frequency that crystal resonator X ₂ has. There is a drawback that a stable oscillation start-up cannot be obtained.

In view of the above points, an object of the present invention is to provide a crystal oscillation circuit with stable oscillation start and low power consumption.

According to the present invention, it is possible to obtain a crystal oscillation circuit that uses one CMOS inverter at the start of oscillation and, after the oscillation becomes stable, switches to an oscillation circuit in which three inversion circuits are connected in series.

Next, one embodiment of the present invention will be described with reference to FIGS. 3a and 3b.

As shown in FIG. 3a, the inverter _I1 is constructed by connecting n-channel MOS transistors _Q9 , _Q10 and p-channel MOS transistors _Q11 , _Q12 in series between the power supply _-VD and ground. The output O ₁ of this inverter I ₁ is taken out from the intermediate connection point between transistors Q ₁₀ and Q ₁₁ . This output Q ₁ is led to the output point O ₂ of the oscillation circuit. Output point O ₂ is connected to MOS transistors Q ₁₀ and Q ₁₁ via resistor R ₆ and crystal oscillator X ₃ .
A return connection is made to the gate of Also, inverter I ₂ ,
I ₃ and I ₄ are connected in cascade and the first stage inverter I ₂
Similar to the inverter _I1 , the input of the inverter is a feedback input of the signal from the output point _O2 via the resistor _R6 and the crystal oscillator _X3 . The output O ₃ of the inverter I ₄ is connected to the output point O ₂ . Here, in the inverter _I1 , the control signal φ is applied to the gate of the n-channel
MOS transistor _Q9 and a p-channel with a control signal in opposite phase to φ applied to the gate.
MOS transistor _Q12 is provided in series,
These transistors receive control signals φ,
The inverter I1 acts as a switch depending on the current, and when both are conductive, the inverter _I1 becomes active. Similarly, in the inverter _I4 , an n-channel MOS transistor _Q17 with a control signal applied to its gate and a p-channel MOS transistor _Q20 with a control signal φ applied to its gate are connected in series between the power supplies. It works as a switch and controls the operation of inverter _I4 . inverter
The operating periods of I ₁ and I ₄ are complementary. The control signal φ is obtained from φ _C through one stage of inverters and two stages of inverters, respectively, as shown in FIG. 3b.

First, in the initial state, the φ side High level side is
It is at low level. In this state, Q ₉ , Q ₁₂
is on and Q ₁₇ and Q ₂₀ are off, so the oscillation is caused by 1 of Q ₁₀ and Q ₁₁
Starting with the stage inverter type. After a while, after the internal circuit has stably operated, if a low level signal is sent from the control pulse input, the level of φ is reversed, Q ₉ , Q ₁₂ are turned off, and Q ₁₇ ,
Since _Q12 is turned on, oscillation will continue with the 3-stage inverter type. In this circuit, the 1-stage inverter only needs to use a transistor with sufficient gm to stabilize the start of oscillation.The power consumption is high at the start of oscillation, but after that it switches to the 3-stage inverter, so there is no problem. Because of its low power consumption, this crystal oscillator circuit has the advantages of a single-stage inverter and a three-stage inverter, with stable oscillation start and low power consumption. Here, the method of obtaining the control pulse φ _C is to detect the rise of the power supply, store this level in a flip-flop, etc., and then output the counter after the internal circuit operates.
This can be obtained by extracting a signal that inverts this flip-flop using the output of the ROM.
Alternatively, the output of a time constant circuit or delay circuit that starts operating when the power supply is turned on may be used.

As described above, according to this circuit, by switching between the 1-stage inverter type and the 3-stage inverter type using control pulses, it is possible to extract only the strengths out of the contradictory strengths and weaknesses of the two, and as a result, oscillation starts. A stable, low power consumption crystal oscillator circuit can be realized.

Next, another embodiment of the present invention will be described with reference to FIG.

In the above-mentioned embodiment, one-stage and three-stage inverters were prepared separately in the circuit, but in this embodiment, they are used in common, saving one stage of inverter.

The output N ₁ of the first stage inverter I ₁₁ is led out to the output OUT via the node N ₂ via the n-channel transistor Q ₃₄ and the p-channel transistor Q ₃₅ to which the control signals φ and are input, respectively. Further, the output N ₁ is inputted to the second stage inverter I ₁₂ via an n-channel transistor Q ₃₀ and a p-channel transistor Q ₃₁ to which the control signal and φ are input, respectively, to their gates. The output of inverter I ₁₂ is directly inverter
_I13 is supplied to the input of the inverter I13, and the output of the inverter _I13 is connected to the n-channel transistors _Q32 and p with the control signal and φ inputted to the gates, respectively.
It can be led to the output OUT via the channel transistor Q ₃₃ and the node N ₂ .

Here, the control signal φ is the same as that in the embodiment shown in FIG. 2, and first, during the oscillation start period, φ is at a high level and is at a low level, so that transistors Q ₃₄ and Q ₃₅ are conductive, and transistors Q 30 to Q ₃₀ are turned on.
Since Q ₃₃ is non-conducting, the circuit operates using one stage of inverter I ₁₁ . Next, when a stable state is reached, φ becomes a low level and becomes a high level, transistors Q ₃₀ to _{Q 33} become conductive, and transistors Q ₃₄ and Q _{35 become} conductive.
becomes non-conductive, resulting in a configuration in which inverters I ₁₁ to I ₁₃ are connected in cascade.

Note that when switching from a 1-stage inverter to a 3-stage inverter, all transistors Q ₃₀ to _{Q 35}
It is also good to provide a period during which the conduction occurs. In addition, Q3
When 0, Q31, Q32, and Q33 are off,
Since the gate voltage of I ₁₂ is not determined, a through current flows through I ₁₂ and I ₁₃ , but this usually does not cause a problem since only I ₁₁ operates during the time when oscillation starts. However, if there is a possibility that a voltage drop may occur, the gate voltage of _I12 should be fixed to the power supply or ground potential, or the gate voltage of _I12 and
Adding a gate to disconnect I ₁₃ from the power supply can also be a solution.

It can thus be understood that the circuit of this embodiment also operates in the same manner as the embodiments described above.

Note that the present invention is not limited to the above-described embodiments, and can be applied to piezoelectric vibrators other than crystal, for example. Further, the use of the first-stage and third-stage inverters may be switched in any manner.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional crystal oscillation circuit, FIG. 2 is a circuit diagram showing another conventional crystal oscillation circuit, and FIG. 3a is a circuit diagram showing a crystal oscillation circuit according to an embodiment of the present invention. FIG. 3b is a block diagram showing a system for obtaining control signals, and FIG. 4 is a circuit diagram showing another embodiment of the invention. Q ₁ , Q ₃ , Q ₅ , Q ₇ , Q ₉ , Q ₁₀ , Q ₁₃ , Q ₁₅ , Q ₁₇ ,
Q ₁₈ , Q ₃₀ , Q ₃₂ , Q ₃₄ ... n-type transistor, Q ₂ ,
Q ₄ , Q ₆ , Q ₈ , Q ₁₁ , Q ₁₂ , Q ₁₄ , Q ₁₆ , Q ₁₉ , Q ₂₀ ,
Q ₃₁ , Q ₃₃ , Q ₃₅ ... p-type transistor, R ₁ , R ₃ ,
R ₅ , R ₁₃ ... Feedback resistor, R ₂ , R ₄ , R ₆ , R ₁₆ ...
Output resistance, C _{1 to 6} ...Capacitance, X _{1 to 4} ...Crystal oscillator.

Claims (1)

[Claims] 1 comprises a piezoelectric vibrator, at least three CMOS inverters, and a circuit switching means, and the circuit switching means is configured to switch between the piezoelectric vibrator and one stage at the start of oscillation.
A first closed loop is formed with a CMOS inverter as the main component, and during continuous oscillation after oscillation has started, a first closed loop is formed with a three-stage CMOS inverter with the piezoelectric vibrator and input/output connected in series as the main component. An oscillation circuit characterized in that the circuit is switched to form two closed loops.