SU1667074A1 - System for checking electronic devices - Google Patents

Abstract

The invention relates to computing and can be used in systems for the automatic control of integrated circuits, as well as digital blocks and devices during their production and operation. The aim of the invention is to improve the speed of the device. For this purpose, a main memory unit, a one-shot recording device and an address counter are entered into the device containing the test task and reaction analysis block, the clock generator, the comparison block, the pulse distributor, the pulse shaper, the pulse counter, the shift register and the correction block. 4 il.

Description

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The invention relates to computing and can be used in systems for the automatic control of integrated circuits, as well as digital blocks and devices during their production and operation.

The aim of the invention is to improve the speed of the device.

FIG. 1 shows a structural diagram of a system for monitoring electronic devices; figure 2 - scheme of the one-shot recording; on fig.Z - diagram of the correction unit; 4 shows an algorithm for the operation of a unit for setting tests and analyzing reactions.

The system for controlling electronic devices (Fig. 1) contains a block 1 for setting tests and analyzing reactions (analogous to the functional purpose of the prototype digital computer), the output of the test feature and the first and second information outputs of which are connected respectively to the trigger input of the clock generator 2, information inputs of block 3 comparison and monitored device. The second information input of the comparison unit 3 is the input of the device for connection to the output of the monitored device (object). The output of the clock generator 2 is connected to the input of the pulse distributor 4, the first, second and third outputs of which are connected respectively to the control input of the comparison unit 3, the synchronization input of the pulse driver 5 and the write input of the shift register 6. The output of the comparison unit 3 is connected to the information inputs of the shift register 6 and the pulse generator 5, the first output of which is connected to the counting inputs of the shift register 6 and the counter 7. The second output of the driver 5 is connected to the stop input of the clock generator 2. input do stop block 1

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and the overflow of the counter 7, and the information output of the counter 7 is connected to the information input of the correction unit 8 and the data input of the random access memory 9.

The output of the shift register b is connected to the control input of the correction unit 8, the control input of the one-shot 10 recording and the counting input of the address counter 11. The output of the correction unit 8 is connected to the third information input of the comparison unit 3. The output of the address 11 counter is connected to the address input of the block 9. A recording input of which is connected to the output of the single-vibrator 10. The output of the block 9 is connected to the information input of the block 1 for setting tests and analyzing reactions.

The RAM block 9 can be implemented on chips such as 155RU7 with a bit on data buses equal to the size of the counter 7.

The address counter 11 may F JTB is made on chips of the type 155I1 / with a width equal to the number of reference channels. A single-write 10 is made on the chip 12 type 155AH (figure 2), in addition to the chip 12, the one-shot 10 contains a resistor 13 and a capacitor 14.

The correction block 8 is similar to the correction block of a known object.

The correction block contains (Fig. 3) triggers 15, elements AND 16 and a decoder 17, the outputs of which are connected to the first inputs of the corresponding elements AND 16, the second inputs of elements AND 16 are interconnected and are the control input of the correction block 8, and the outputs of the elements And 16 are connected to the installation inputs 1 of the corresponding triggers 15.

The system works as follows.

At each step of the test sequence, unit 1 reads the next test code set consisting of 1 and 0 from its memory and outputs this code to the monitored device. Then block 1 transmits to reference block 3 a reference code set corresponding to the desired response signals of the monitored device. At the end of the transient processes in the controlled device, the unit 1, which sets tests and analyzes reactions, starts generator 2. which starts generating a sequence of clock pulses.

By running generator 2, unit 1 is freed from the process of monitoring this device. Clock pulses from the clock generator arrive at the distributor 4 pulses. The first clock pulse is fed to the control input of the comparison unit 3, the second input of which is connected to

output controlled device. As a result, the first clock pulse permits the passage of signals from the output of the monitored device to the comparison unit 3, where they are compared with the reference code set. In block 3, a code is generated containing 0 in those bits where the output of the monitored device matches the reference signal, and 1 in those bits. where the match does not occur. The second clock pulse is fed to the input of the recording of the shift register 6 and allows overwriting of the contents of the comparison block 3 into the last one.

5 The third and subsequent clock pulses from the distributor 4 pulses are fed to the synchronization input of the imaging unit 5, the input of which is connected

0 to the output of block 3 comparison. If the signals of the monitored device coincide with the reference code set, the second output (comparison) of the driver 5 generates a signal that prohibits further operation of the clock generator 2 and enters the stop input of block 1. If the signals of the monitored device do not match the reference code set, a non-match signal is generated on the first output

0 shaper 5. For each pulse Shaper shaper 5, the contents of the shift register 6 is shifted by one bit, and the contents of the counter 7 is increased by 1, If the output of the register 6

5 signal 1 appears, which indicates that the signal of the monitored device does not match the reference one, then this signal from the output of register 6 goes to the counting input of counter 11, increasing its content in 1, and to the input one of the vibrator 10. The content of the counter 7 corresponding to at this moment, the digit number of the code in which the mismatch occurred is entered in block 9 through the signal from the output of the one-shot 10

5 address at the output of the counter 11.

When the next mismatch occurs, i.e. G at the output of register 6, again this cycle is repeated and the content of counter 7 is recorded in the next cell of block / a 9.

The shifts in the contents of register 6 continue until the address of the last non-match of the least significant bits is transferred to block 9. After that, the remaining bits of the codes are not polled, the clock 2 is turned off and a stop signal is received in block 1. This is ensured by the fact that with each mismatch of code bits, the corresponding bit is corrected in block 3 comparisons, i.e.

the state of this bit is forcibly set to O. using signals from correction block 8 (FIG. 3).

The contents of the counter 7 are fed to the input of the decoder 17, therefore at each moment of time there is a resolving potential at one of the elements 16. And the occurrence of 1 at the output of the register 6 triggers the input Setting 1 of the corresponding trigger 15. The signal from the output of this trigger 15 goes to block 3 compare and correct it, i.e. translates from 1 to O.

Thus, as the contents of the register 6 advance, a successive correction of the bits in which the non-comparison takes place occurs.

The algorithm of the unit for setting tests and analyzing reactions is shown in Fig. 4.

On the Stop signal, block 1 of setting tests and analyzing reactions sequentially reads the contents of block 9, starting from the first address to the address with the content equal to 0.

The contents of the cells of block 9. other than O correspond to the number of the discharge on which the discrepancy was recorded, the contents of cell 9 equal to 0, block 1 perceives as the absence of non-matching bits and proceeds to the analysis of the results or the formation and issuance of a test set.

Claims (1)

The invention includes a system for monitoring electronic devices, comprising a test setting and reaction analysis unit, a clock generator, a comparison unit, a pulse distributor, a pulse shaper, a shift register, a pulse counter and a correction unit, the test feature output and the first information output of the test setting unit analysis of the reactions are connected respectively to the trigger input the generator and the first information input of the comparison unit, the second information output of the test task and reaction analysis block and the second information input the comparison unit is the output and input of the device for connecting the control object to the input and output respectively, the output of the clock generator is connected to the input of the pulse distributor, the first, second and third outputs of which are connected respectively to the control input of the comparison unit, the synchronizer input of the pulse former and the recording input shift register, the output of the comparison unit is connected to the information inputs the shift register and pulse generator, the first output of which is connected to the counting inputs of the shift register and pulse counter, the second output of the pulse generator is combined with the pulse counter overflow output and connected to the stop inputs of the clock generator and the test task setup unit and the analysis of the pulse counter information output connected to informational the input of the correction unit, the output of the shift register is connected to the control input of the correction unit, the output of which is connected to the third information input of the comparator unit, that, in order to improve speed, it contains a memory block, a single recording vibrator and an address counter, the counting input and the output of which are connected respectively to the shift register output and the address input of the RAM block, the data input, the recording input and the output of which are connected respectively, with the information output of the pulse counter, the output of the one-shot recording and the information input of the unit for setting tests and analyzing reactions, and the input of the one-shot recording is connected to the output of the shift register. figure 1 15/5 Uh g ABOUT ,. 3 I G6 (CSS} extracting RAM from block 1 next test dialing Issuance, tncpedaao) test set on a controlled device Selection from the RAM block the next reference recruitment The issuance (transfer) of this set to this device is shamed 3 Wrike and issue wxo / to. Run on generator / tag any / itcoff OmffaHiie interrupts from the signal „Stop from counter 7 that vifHafMami / HS. will namtit iftui ptftarff inotat Processing npepttffairuf na signal. Stop Reading - Regular Ion of RAM 9 (End J signal. Nndigvia nnzr M .t ctlnadtHut- in “yo da aouigyiiatt ilftlimn