SU1665479A1 - Device for controlling n static frequency converters parallel connected at their inputs and outputs - Google Patents

Abstract

The invention relates to electrical engineering and can be used to control N converters connected in parallel along the input and output. The aim of the invention is to expand the functionality of the device. Depending on the magnitude of the load, a corresponding number of transducers are included in parallel operation. The number of parallel converters determines the first logic block. However, in operation it is necessary to disconnect the transducers for repair and maintenance. Accounting for disconnected converters is carried out automatically due to the voltages entered by the relay and the second logic unit. 3 il.

Description

The invention relates to electrical engineering and can be used to control N converters connected in parallel to the input and output.

The purpose of the invention is to enhance the functional reliability of the device.

FIG. 1 and 2 shows the scheme of the proposed device; in fig. 3, 4 - possible options for the construction of the first and second logical blocks.

A device for controlling the on and output parallel by input and output N static frequency converters, each of which contains a controlled rectifier 1, the output of which through a filter 2 and a current sensor 3 is connected to the input of the inverter 4, the first power switch 5, converter input terminals with power input of rectifier 1, second power switch 6 connecting inverter 4 output with converter output terminals, rectifier control unit 7, the output of which is connected to the first input of the first element AND 8, whose output connects not with control input of rectifier 1, comparison unit 9, one input of which is connected to the output of current sensor 3, output connected to input of control unit 7, control inputs of the first 5 and second 6 power switches and second input of the And 8 element and form the enable enable input, the adder 10, the inputs of which are connected to the outputs of the current sensor 3 of each converter, the first 11 and second 12 dividers, made controlled by N-1 control inputs 13 and 14 and N and N-1 respectively division, first 15 and second 16 comparators, ist chnik reference voltage 17, the first 18 and second 19 pulse shapers.

oh oh ate

4 vl h

the second 20 and third 21 elements are AND, the first 22, second 23 and third 24 OR elements, delay element 25 and logic block 26, having first 27 and second 28 inputs and N outputs.

The output of the adder 10 is connected via the divider 11 to the direct input of the comparator 15 and the second inputs of the comparison units 9, and through the divider 12 to the inverse input of the comparator 16. The inverse input of the comparator 15 and the direct input of the comparator 16 are connected to the reference voltage source 17 . The outputs of the Comparators 15 and 16 through the formers 18 and 19 pulses and the first inputs of the elements OR 22 and 23, as well as through the first inputs of the elements AND 20 and 21 and the second inputs of the elements OR 22 and 23 are connected respectively to the first 27 and second 28 inputs of the logic unit 26 The outputs of the elements OR 22 and 23 are connected through a series-connected element OR 24 and a delay element 25 connected to the second inputs of the elements 20 and 21. The outputs of the logic unit 26 are connected to the enable inputs of the respective converters. The control unit additionally includes N voltage relays 29, the inputs of which are connected in parallel to the inverter inputs 4 in the converters, and a second logic unit 30 having N inputs and N-1 outputs that is connected between the voltage relay outputs 29 and control inputs 13 and 14 dividers 11 and 12. The element OR 22 is provided with a third input, which is the control input of the control device. The first logic unit 26 is configured with N outputs, which are connected to the enable inputs of the inclusion of the respective converters. The state of the logical variables Qi Q2, ..., QN at the output of block 26 is determined by the expression

Qj / 1, Oh, if j V

, 2N

where V is the difference between the number of pulses received on the first 27 and second 28 inputs of block 26.

The second logic block 30 is described by a function

YK G1. if Xj -1;

Oh, if K 2, Xj - 1

K 1,2N-1

where Xj, YK-respectively, the logical functions at the j-th input and the K-th output of the logic unit 28.

A possible variant of the first logical block 26 is shown in FIG. 3 and includes a reversible counter 31, the summing and subtracting inputs of which form the first 27 and second 28 inputs of the logic unit 26, respectively, and the outputs through the decoder 32 are connected to the inputs 1, 2, ..., N-1 of the elements OR 33. The outputs the latter, as well as the Nth output of the decoder 32, form the outputs of logic block 26,

An example implementation of the second logic unit 30 for N 4 is shown in FIG. 4. The scheme contains elements 2I 34-39, 2ILI 40-42, ZILI 43. Other variants of the implementation of block 30 are also possible.

The operation of the proposed control device is carried out as follows.

The device automatically sets up, depending on the size of the load, the necessary number of parallel converters and a uniform distribution of power between them. Turning on

5 transducers occur when a pulse is applied to the free input of the element OR 22. At the output of the latter, a pulse appears that goes to the summing input of the reversible counter 31.

0 record of the unit in the first bit of counter 31 and its transfer to the first bit of decoder 32. The bit I of counter 31 is equal to the nearest integer for log2N. Logical unit from the first output of the decoder

5 32 through the N input element OR 33 is fed to the enable input of the first converter. Power switches 5 and 6 provide the connection of the converter with the supplying f 1 and output network fa, and the unit

0 7 control brings the converter to the operating mode. Relay 29 in the first converter triggers and causes the appearance of a logical unit at input Xi of logic unit 30. In accordance with the algorithm functioning of this unit, at its outputs YL Ya, ..., YN-I, the levels of logical zero will remain. Therefore, the transfer ratio of the divider 11 is 1, and the divider 12 is the gain of the basic operational amplifier.

With an increase in the load of the power supply system, the necessary number of transducers are introduced for parallel operation. Turn on the next

5 transducer occurs when the condition

one

m

-

(one)

where IK is the input current of the inverter in the k-th converter;

IHOM is the rated current of the inverter;

m is the number of parallel converters.

A signal proportional to the left side of inequality (1) is formed by the divisor 11, the IHOM value is set by the source of the reference voltage 17.

When the inequality (1) is fulfilled, the signal of a logical unit appears at the output of the comparator 15. This signal through the driver 18 and the element 11 is fed to the summing input of the reversible counter 31. The binary word at the output of the latter acquires a new value, leads to the appearance of a logical unit at that output of the decoder 32, the number of which corresponds to the included converter.

Disconnection of the corresponding converter occurs when the condition is 1 m

 & - (2)

the left part of which is formed by the divider 12.

In this case, a logical unit signal appears at the output of the comparator 16 and a pulse is applied to the subtracting input of the counter 31. The corresponding output of the logic unit 26 is zeroed, which causes the converter to turn off.

After each command to enable or disable the transducers, the comparators 15 and 16 are re-polled. To ensure the stable operation of the system, this survey is performed with some delay determined by element 25. If during this time any of the comparators has not changed its state, then a command is issued to turn on (or turn off) another converter. The pulses on the first 27 and second 28 inputs of the logic unit 26 arrive as long as one of the inequalities (1), (2) is fulfilled. As a result, the number of outputs of the logic block 26, at which the levels of the logical unit are present, is determined by the difference between the number of pulses received at the first 27 and second 28 inputs of the block 26.

The transmission coefficients of the dividers 11 and 12, specifying the left-hand sides of inequalities (1) and (2), respectively, are determined by the number of closed keys in the feedback. The number of closed keys 13 and 14 in dividers 11, 12 is always one less than the actual number of converters switched on in parallel. This correspondence is provided by logic block 30 having N inputs and N-1 outputs. According to the algorithm of its operation, a logical 5 unit at the output YK appears only if the levels of the logical unit are present at (k-1) inputs, for example There are levels of logical units at the inputs Xi, Xa, X4, then logical units will be at the outputs.

Suppose that a first transducer is in operation, and the load has reached a value that requires the inclusion of another

5 converter. In this case, it is possible that the second transducer is brought into reserve or is under preventive inspection or repair.

After forming the command to enable the converter appears.

. logical unit at the output of 02 loopy unit 26. Since the inclusion of the second

converter did not happen then later

some time determined by the element

5 25, a second pulse passes to the first 27 input of logic block 26, which causes the appearance of a logical unit at the output Oz. The third converter is put into operation, which is signaled by the logic

0 unit at the output of relay 29 of this converter. The corresponding switches 13 and 14 of the dividers 11 and 12 are closed and their transfer coefficients change. Uniform load distribution

5 between m parallel-working converters is performed as follows.

Signals proportional to the input currents of 1K inverters 4, from current sensors 3

0 arrive at the adder 10 and further on dividers 11 with a transfer ratio of 1 / m. At the output of the divider 11, a signal is generated that is proportional to the arithmetic mean of the currents k. This signal is compared by the nodes 9 with the output signals of the current sensors 3. The signals at the outputs of the comparison nodes 9 in the control units 7 are added to the error signal of the main control loop by the output voltage. As a result, the control angle ak for the k-th controller is the sum of the two components

5 sgk GO + Dock,

where Gb is the component determined by the deviation of the output voltage, the group of transducers from the specified value;

Varnish is a component determined by the current IK deviation from the arithmetic mean of all currents.

 -n & "The supply voltage of the UdK inverters supplied from the outputs of the filters 2 are monotonically decreasing functions of the angles ck. Therefore, if the current k becomes larger (less) than the value of 0, then the Luck component increases (decreases), increasing (decreasing) the angle of control "k. As a result, the voltage UdK decreases (increases), reducing the magnitude of the mismatch (k - lo) to zero. The inverters are disconnected by applying a pulse to the input to the zero setting of the counter 31. The N zero of the decoder 32 and, accordingly, the enable inputs of the converters are zeroed by the Print.

A positive feature of the proposed device is that it ensures that the transmission coefficients of dividers correspond to the actual number of concurrently operating converters. At the same time, the procedure for the repair of transducers or their routine inspection is essentially but simplified, since there is no need to make complex switchings to ensure the control algorithm. It is enough to block the enable inputs of the respective transducers. The control unit, without interfering with its structure, will automatically ensure that the required number of conversion gels is introduced into parallel operation, which significantly increases the reliability and convenience of operating the power supply system based on a group of transducers.

Claims (1)

Invention Formula A control device is connected in parallel by the input and output N static frequency converters, each of which consists of a first power switch connected in series, a controlled rectifier, a filter, an inverter and an ayur power switch containing a control unit, the output of which is connected to the first the input of the first element AND whose output is intended to be connected to the control inputs of the controlled rectifier, the comparison unit, one input of which is connected to the output of the current sensor whose inputs are intended cheny for incorporation between the power input of the inverter and the power output of the controlled rectifier, the output of comparator unit connected to the input of the control unit, the outputs of the first logic block designed for connection to respective control inputs of the first and the second power switch of each of the N static converters and connected to the second inputs of the corresponding first elements And, the adder, the inputs of which are connected to the outputs of the current sensors each static converter, the first and second dividers, made controllable with N-1 control inputs and, respectively, with N and N-1 division stages, the first and second comparators, the source oopornogo voltage, the first and second pulse shapers, the second and third elements And, the first, second and third elements OR, the delay element, and the output of the adder through the first divider connected to the direct input of the first comparator and the second inputs of the comparison units, and through the second divider to the inverse input of the second comparator, the inverse input of the first and the direct input of the second comparators are connected to the source of the reference voltage, the outputs of the first and second comparators through the first and second drivers pulses and the first inputs of the first and second elements OR, and also through the first inputs of the second and third elements AND and the second inputs of the first and second elements OR are connected respectively to the first and second inputs of the first logical block that implements the following logic functions: QJ / 1, if j ≤ 0, if j g, where j is the number of the corresponding output from 1 house; QJ is the logical state at the jth output; g - the difference between the number of pulses received at the first and second inputs of the first logic unit, the outputs of the first and second elements OR are connected through the third element sequentially connected and the delay element is connected to the second inputs of elements AND, it is known that, in order to increase the functional reliability, N voltage relays and a second logic unit equipped with N inputs and N-1 outputs, voltage relay inputs are connected in parallel to the inverter inputs of each of the N static converters, and the voltage relay outputs are connected via the second logic unit to the corresponding control inputs of the first and second dividers; the first OR element is provided with a third input, which is the device control input, the second logic unit is described by a function JK I. if K 2 Xi -1, N Oh, if K Y Xi - 1, where K 1,2N-1; Xi, JK are logical functions at the 1st input and Km output of the second logic block, respectively. a be pgrs p grs Fie.2 Fig.Z FI.4