SU1432698A2 - Group frequency converter - Google Patents

Abstract

The invention relates to a power converter technology and is designed to supply a load of the increased frequency based on parallel-working thyristor converters and frequency. The purpose of the invention is to increase functional reliability. The adder 22 with one input and output is connected between the output of the comparison unit 6 and the input of the controller control unit 4.

Description

(L

with

N

with

00

fNJ

:

the other input of the adder 22 through the nonlinear element 21 is connected to the output of the additional comparison node 20, one input of which is connected to the output of the current sensor 5 of the corresponding block and the other input is connected

with reference voltage source 12 common to all converter units. The proposed device allows to exclude current overloads that can lead to a break in the power supply of the consumer, 1 sludge.

one

The invention relates to power converter technology, can be used in centralized power supply systems of an enterprise based on parallel to existing thyristor frequency converters and is an improvement of the invention according to the authors. St. No. 1267563.

The aim of the invention is to increase the functional reliability and the path of country overloads in dynamic modes,

I The drawing shows a pre-xijeHHoro converter circuit.

; The group converter consists of N blocks, each of which is co-f BpjKKT inverter 1, regulator 2 input – HJoro voltage, filter 3, node ff control regulator, current sensor 5, 6. comparison, adder 7, first 8 and the second 9 voltage dividers, the first 10 and. the second comparator 11, reference voltage source 12, reversible counter 13, decoder 14, N-2 elements OR 15, two power switches 16, and 17, And 18, control key 9, and also the second comparison node 20 is a nonlinear element 21 and an adder 22. The division steps in dividers 8 and 9 are switched by a controllable key 19.

The device works as follows.

The power consumed by the inverters is:

3

and

dj j-dj

(j, n)

Uj. - power supply voltage of the j-th InJtch .yyy1 .- –r оj-iTj lea iu ("o f OMSfT (

 -di

the rotor removed from the filter capacity 3;

is the average current required by the jth inverter.

2

The value of Ij: depends on the equivalent active resistance Rj. DC circuit of the corresponding inverter. Taking into account that the voltages Uj differ little from each other due to the smallness of Rj; then, using them as a regulating parameter, one can achieve the specified values of the currents Ij-, which must be consumed with the required load distribution. I

Ij signals; proportional to the values of consumed currents Ij-, from the outputs of sensors 5, which can be made in the form of shunt, are fed to the inputs of adder 7, the output of which is the signal It

to

 Ij- This signal is input JH J

for the first 8 and second 9 dividers, performed according to the inverting scale amplifier. The output of the first divider 8 is obtained

 1 D- is the signal I, - Z Ij - which was I "J is reference in the system of uniform

load power distribution between currently included inverters. Comparison node 6 j-ro converter generates a mismatch signal u (u Ij 1 proportional to the deviation of the current value of the current consumed by the j-th bridge

on the average arithmetic value of the currents consumed by the inverters currently operating.

At the output of the second comparison node 20 of the converter, the signal ijHj lo Idj 0 takes place, a signal corresponding to the value of the current consumed by a separate inverter in the nominal mode. It is given by source 12 and is shared.

 1432698

for all N blocks. nonlinear element 21, the signal ujuj is fed to one of the inputs of the adder 22, to the other input of which the error signal & U comes. At the output of the adder 22, a signal is generated

common common to all converter; oti is the value of the additional adjustment angle determined by the mismatch, the Control Unit A operates in such A (U: & nj1 + К ",. ДЛ. (I, .- I,) + way, that for those converting" К (I - I) which is the current value

     consumed current exceeds I, (i.e.

) the value of ot j O and, therefore, the voltage applied to the input of the corresponding inverter Uj; ,

tse with jj

where Ktsd - the transfer coefficient of the nonlinear element.

In particular, when used in

As the last diode connected - 15 is reduced, which leads to a cathode reduction to the output of node 20, comparing current Ij and decreasing absolute magnitude, the following equality takes place: ... mismatch value AjU. On the contrary, when I (j- with I, we have 6 (Us О, and the value of the additional angle i О, which 20 leads to an increase in the current Ij- and a decrease in

ne

Iji

about cij

Then in nominal and close to it mode K, O, and. at the output of the adder 22, an error signal will be generated & fWj Ij; I / (U °, which is fed to the input of the control unit 4 of the constant voltage regulator 2. The regulator can be made on the basis of a direct current inverter – ZO converter and the nature of the connection unmanaged expirator, as well as to the base of the controllable top ten.

In the transducers connected to the transducer, a parallel operation is performed, the initial signal-equalizing signal V, which the control unit 4 doesn’t allow, can be connected to switch keys 16 and 17

This is in the regulation of the value of the output-master unit.

At the inputs of the first 8 and second 9 controlled dividers, the sleep voltages of the regulators 2 are formed in order to stabilize the output voltage of each transducer. In this case, bju mismatch signals; supplied from the outputs of the adder 22 are folded in the control units 4 with the error signal (AND the main control loop (i.e., the feedback signal of the output voltage stabilization system).

When using a constant voltage of controlled rectifiers as a regulator 2, the control angle of the valve j-ro is equal to

oij ci,

.

where Ы | 5 is the component of the angle of control determined by the stabilization of the output voltage, and this component is common to all the transducer; oti is the value of the additional control angle determined by the mismatch, and the control is operating in such a way that it is reduced for those, which leads to a decrease in the current Ij and a decrease in the absolute ... mismatch AjU. On the contrary, when I (j- with I, we have 6 (Us О, and the magnitude of the additional angle i О, which leads to an increase in the current Ij- and a decrease in the absolute value of the mismatch.

Thus, the condition of uniform distribution of the load power between parallel-converting units operating at a given time is fulfilled.

The device is automatic, depending on the magnitude

power-on)

Of the entire set, the first block is the master, the rest (N-1) are the slave. Inclusion of the group pre-block.

0

Q

5 o

five

At the inputs of the first 8 and second 9 controlled dividers are formed with 1 - responsibly signals 1 --- Ij- and

 to v.ri J

 1 to

T- - IJ-Z-Ij; - Comparison I, and 1,

implemented by the first 10 and second 1 comparators respectively. As the load increases, the inequality I, 1 + D1, is fulfilled, and at the output of the First Comparator 10 a single level signal is generated, with the advent of which the algorithm of switching on the next unit to parallel operation is implemented. As the load decreases, the inequality Ij TO –D1 is fulfilled and the output of the second comparator 1 is a single-level signal, which directly shuts off one of the group of parallel-running units. Here & M 5

values that broaden the range of constancy of the structure of the power part of the converter. They are set by the bias voltage U applied to the direct input of the first comparator 10 and the reverse input of the second comparator 11. Their introduction is caused by the fact that 1, n 1 have a certain error, determined by sensors 5, adders J7 and dividers 8 and 9. j The enable / disable algorithm for an individual converting unit is implemented as follows. i The signal of a single level from the output; the first 10 (second 11) comparator I is fed to the summed-up (subtracting) input of the reversing counter 13,; whose width is 1 - the nearest integer for logi (N-l). A new binary word, the value of which determines the number of blocks included in parallel operation, from the output of counter 13 is fed to the input of the decoder 14, the single signal at its corresponding output through logic elements 15 provides the level resolution on the keys 16 and 17 and elements 18 of the corresponding number parallel working blocks. These levels provide the necessary division factors of the controlled dividers 8 and 9 by closing the corresponding keys 19, At the initial moment of starting the i-th section of the converter, the mismatch values L (u, u, u (U will be comparable to | 1 (d, since 0 However, when the value of 1 starts, the nonlinear element 21 (K cd 1) works. Then the mismatch value is u (U, (, 1. Start

326986

continues under the condition (ujU,): jUg, since the values 1 and I are close to gmi. This eliminates the significant current overloads of the switched on unit. In the future, the system for distributing currents between the converter sections operates at O, excluding the component 10 (H-.

Thus, the introduction of a non-linear element group frequency converter into the circuit, as well as an additional comparison node and a cummator, improves functional reliability when a separate converter unit is turned on by eliminating current overloads that can lead to overload

20

Claims (1)

consumer leap. Invention Formula Group frequency converter according to avt. No. 1267563, characterized in that, in order to increase functional reliability by eliminating overloads in dynamic modes, each block is provided with an additional comparison node, nonlinear element and adder, the output of the comparison node is connected to the input of the regulator control node through the first input of the adder, the second input of the adder through a non-linear element is connected to the output of an additional comparison node, one input of which is connected to the output of the current sensor of the corresponding block, and the second input is connected to the source of the reference voltage no.