SU1539800A2 - Integrator with automatic zero level correction - Google Patents

Abstract

The invention relates to automation and computer technology, intended for use in automatic control systems. The purpose of the invention is the expansion of the class of tasks. The integrator contains a series-connected integrating amplifier 1, a summing amplifier 2, a comparator 3, a reversible counter 4, a digital-to-analog converter 5 (DAC), a reference frequency generator 6, disconnecting switches 7-10, two analog inverters 11,12. Due to the presence of the negative feedback voltage U _DAC continuously monitors the output voltage of the integrating amplifier 1, wherein a difference U _int - U _DAC does not exceed the first least significant bit DAC. At the end of the pause, one of the keys 7 or 8 opens, the arrival of pulses of the reference frequency from the generator 6 is stopped. In the subsequent integration cycle, the voltage at the output of the DAC 5, equal to U _int – U _int , is applied to the integrating amplifier 1 to compensate its zero level offset. 1 il.

Description

The invention relates to automation and computer technology and is intended for use in automatic control systems.

The purpose of the invention is the expansion of the class of tasks.

The drawing shows an integrator circuit with automatic zero level correction.

The integrator contains a series-connected integrating amplifier 1, the first inverting input of which is the first integrator input, a summing amplifier 2, a comparator 3, a reversible counter 4 and a digital-to-analog converter 5, the output of which is connected to a non-inverting input of the integrating amplifier, a reference frequency generator 6, disconnect switches 7- 10 and two analog inverters 11 and 12.

The integrator works as follows.

When a signal appears More duration voltage U _{eX) is} supplied to the input of the inverter 11 and from its output is fed to the input of the inverting amplifier 1 in the input voltage -Uox,.

Signal Duration More

- t, - t ₀₁ , Η) where t ₀₁ is the time moment of the leading edge of the pulse More;

t, is the time moment of the trailing edge of the pulse More.

At the same time, a bias voltage is present at the other input of the integrator. Ik, which, entering the input of the integrating amplifier I, would introduce an error into the integration if the opening switch 9 were open. Then the voltage at the output of the integrating amplifier 11 would increase according to the law and ^ m = - i <-U _6Xl + u _CMi ) dt = i, = ju ^ dt- Ism / * · (2)

As can be seen from formula (2), the voltage at the output of the integrating amplifier consists of two terms

- “yig * <

where C _int is the voltage at the output of the integrating amplifier at zero bias at the second input of the integrator;

U _n is the voltage introducing an error into the integration in the presence of a bias voltage U _{CMj [} at the second input of the integrator.

Thus,

B

= J and _m , L; b * (4) Un 7- $ (-UcM.) ^ T. (5) ^ 01 In the presence of Signal More time-

the wrench 9 is closed and the input of the integrating amplifier 1 receives a voltage of reverse polarity 1 ^and cm <1 »I due to the inversion of the voltage U _CMj , by an analog inverter 12, as a result, the integration error is automatically compensated and the voltage at the output of the integrating amplifier 1 increases in the region

Inc ⁼ j (Chvg, “U cm 2 ⁺ CM ₂ ) dt. (6)

In order to prevent the integration of a direct non-inverted signal in the presence of a signal, the voltage U _gXf is supplied to the control input of the isolating switch 10, which disconnects the integrator input from the input of the integrating amplifier 1.

Similarly, the integration error is automatically compensated for when the Less signal appears.

In a pause, when both signals from the outputs of the industrial controller are absent, bias voltages U _CWi ^and Chey are applied to the inputs of the integrating amplifier 1, respectively, from the integrator's input and inverted bias voltages, i.e. -Ism and -uLm _2> from the outputs of inverters 11 and 12 and at the output of the integrating amplifier 1, the voltage changes according to the law ίο * “L - - j '(7)

This voltage introduces a certain error into the integration during a pause.

One of the basic requirements for a device for integration is a high voltage stability at the output of the device, i.e. at the output of the integrating amplifier 1 during a pause, when integration is not performed. At this time, the disconnecting switches 7 and 8 are closed, and bias voltages and U _CW1 are applied to the inputs of the device,

Suppose that the voltage at the output of the PAP 5 IC _LP at the initial time is zero, the voltage difference ( ^U CM, - ^and cm * - ^and cm, ⁺ and ' _С m ₂ ) causes a change in the output voltage of the integrating amplifier 1 U ^ _HT , which leads to the operation of comparator 3, since the voltage balance is disturbed and U _UFL at the input of summing amplifier 2.

The pulses of the reference frequency from the generator 20 of the reference frequency through the disconnecting keys 7 and 8 begin to arrive at the counting input of the reverse counter 4. The direction of the counting is determined by the sign of the voltage difference 25 < ^and Tsng - and _TsLP ).

As the code increases in the reverse counter 4, the voltage at the output of the DAC 5 U increases. ,,, and at some point in time reaches a value of 30 and ' _it . The difference sign “ ^and DAC) changes to the opposite, and the comparator 3 switches to the opposite state, changing the counting direction of the reverse counter 4.

Code set in the down counter 4, and hence the output voltage of IC _PL begin to decrease. 40

Thus, due to the presence of negative feedback, the voltage and _q dd continuously monitors the output voltage of the integrating amplifier 1, while the difference (U _ННт - 45

- Uq _4n ) does not exceed the first least significant bit of the DAC.

At the end of the pause, one of the keys 7 and 8 opens and the arrival of the reference frequency pulses from the generator 6 stops,

In the next integration cycle, the voltage at the output of the DAC 5, which is equal to Oscnt “ ^and 'and _K t, is applied to the non-inverting input of the integrating amplifier 1, compensating for the shift of its zero level.

Claims (1)

Claim Integrator with automatic zero-level correction according to ed. St. No. 1072062, characterized in that, in order to expand the class of tasks to be solved, two analog inverters, a second, a third and a fourth disconnecting key, are introduced into it, the information input of the second disconnecting key being connected. To the output of the reference frequency generator, the output is connected to the information input of the first a disconnecting key, and the control input with an additional integrator input connected to the control and information inputs of the third disconnecting key and the input of the first analog inverter, the output of which is connected to the first mu additional inverting input of integrating amplifier, a second additional inverting input of which is connected to the output of the third disconnecting switch, a second analog input of the inverter connected to the input of an integrator, connected to the control input of the fourth disconnecting switch connected between the output of the second analog inverter and the third additional inverting input of the integrating amplifier.