SU1269269A1 - Multichannel digital-to-analog converter - Google Patents

Abstract

The invention relates to automation and computing and can be used in multichannel digital-analog measurement systems. The invention makes it possible to expand the functionality of a device containing a source of reference voltages, first, second. and the third keys, the first and second And elements, the control unit, the trigger, the memory register, the integrator, the code in the time interval, due to the introduction of a differentiating unit, two analogue switches, an address counter, an integrating amplifier unit, a current limiting element. I zp f-ly, and € 3 Il.

Description

I

The invention relates to automation and computing and can be used in multi-channel digital-analog measurement systems of automation and computing.

 The purpose of the invention is to expand the functionality through multi-channel information processing.

FIG. I presents a functional diagram of a multi-channel digital-to-analog converter; in fig. 2 is a block diagram of a control block; in fig. 3 - diagrams that show the operation of the converter.

The converter consists of memory register 1, whose input buses are input buses 2, and output chips are connected to code converter 3 in the time interval (PCVI) and to the information input of the trigger 4. The PKVI input is connected to the clock generator 5, and its outputs are connected The first and second inputs of the control block b, the second output of which is connected to the clock input of the trigger A and the clock input of the PCVI 3. The first output of the control block 6 is connected to the inputs of elements And 7 and 8, the second inputs of which are connected to the direct and inverse outputs 4 and the outputs with the control inputs of the keys 9 and 10, respectively, connecting the positive and negative outputs of the source 11 of the reference voltages through an integrator performed on the current supply element on the resistor 12, the amplifier 13 and the feedback element made on the capacitor 14, the third switch 15, differentiating unit 16, containing amplifier 17, resistor 18, integrating amplifier 19 with capacitor 20. Amplifier 19 through resistors 21 and 22 is included in the feedback circuit. Amplifier 17. Output of differentiating unit 16 through current limit vayuschy element Submitted: nny the resistor 23 and the second analog switch 24 is connected to the input unit 25, integrating amplifiers, outputs of which are vyhodnmi schinami device, the first analog switch 26 through the voltage driving resistor element 27 is connected to the second input of the integrator. The device also contains a counter 28 addresses. Control unit 6 is complete on three

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triggers 29-31, the element 32 delay and the waiting one-shot 33.

The device works as follows.

5 In memory register 1, for each address, an infcmation is applied, which is to be converted into a constant voltage at the corresponding output of the DAC. Control numbers alternately by command from second exit

the control unit 6 is rewritten in the PCVI 3, and the state of the discharge carrying the information about the sign is rewritten into the trigger 4, the clock frequency

FJJ (diagram 1, fig. 2) from the output of the clock generator 5 is fed to the input of the PCVI, in which a sequence of pulses of frequency F is formed (diagram 2) by dividing

INPUT1 frequency Fg by 2 (N-digit control numbers).

This sequence enters the input of the control unit 6. and after dividing the trigger into two, it enters

through the second output of the control unit (diagram 3) to the address counter 28, to the clock input of the trigger 4 and to the auxiliary input of the PCVI, where it controls the operation of the additional reversible counter. At a time interval T (correction interval), a control number is loaded into this counter from a memory register, .a. in the time interval T y, (measurement interval), the counter counts the input frequency F in the reverse mode. When the number of pulses arrives at its input, which is equal to the control number loaded into it,

the output of a loan pulse appears, which always lies within the interval T, and is separated from its beginning by a time tf equal (in periods of the frequency FO) to the control number written

in PCVI on the previous correction interval (diagram 4). This pulse arrives at the second input of control unit 6, where a logical signal of duration t (diagram 5), which arrives at the first output of the control unit, is formed from the input pulses.

This signal then passes through AND 7 or 8, depending on the state of trigger 4, which determines the sign of the output voltage. The positive output voltage corresponds to the state O at the output Q and the state 1 at the output Q, while the control signal passes to the output of the element 8 and further to the control input of the key 10, which switches the negative source. reference voltage NIN and includes it. With a negative output voltage, switch 9 is turned on, switching a positive source of voltage reference. Thus, keys 9 and 10 commute the reference voltage of the required sign from the output of source 11 through a large-scale resistor 12 to the input of the measuring integrating amplifier 13 during a time interval, the duration of which corresponds to the converted code x. At the same time, for a fixed time interval T, called the measurement interval, the input voltage of the amplifier 13 through the resistor 27 is supplied with feedback voltage from the output of the corresponding channel using the switch 26. The address buses of this switch are output from the output of the address counter 28 the address code as on the address bus of register 1 of the memory when overwriting the control number X from the memory in the PKVI. The time of the on state of the switch 26 is determined by the control signal from the fourth output of the control block 6, which is supplied to the additional control input of the switch 26. The measuring integrating amplifier 13 to the beginning of the measurement interval has zero initial conditions set by key 15, which is open for the entire measurement interval. During the measurement interval, amplifier 13 integrates two voltages: the reference voltage supplied to the input through switch 9 or 10 and resistor 12, and the output voltage of one of the channels to input to input through switch 26 and resistor 27. In. At the end of the measurement interval, the voltage is set at the output of the integrator, which is proportional to the average value of the currents flowing to the input of the amplifier through the large-scale resistors 12 and 27, . , is the voltage at the output of the amplitudes 13 j 694 T, t is the duration of the measurement and conversion intervals; p p 14 the values of the resistors 27 and 12 and the capacitor 14; UQI, is the voltage source of the reference voltage; output voltage at the output of the corresponding channel. Suppose that at zero voltage at the output of the first channel, the memory at the first address contains some code X corresponding to a positive voltage at the output that is not equal to zero. Then, when the address counter 28 becomes the state corresponding to the first address, this code is rewritten from the memory in the PKVI, where it is converted into the corresponding time interval t (. The control signal from the first output of the control unit 6, equal in duration to this interval, element And 8 goes to the control input of the switch 10, through which the negative reference voltage is fed to the input of the integrating amplifier 13 during the time tj,. Since the feedback voltage from output 1 is zero, then by the end of the measurement interval n of the channel, the voltage at the output of the amplifier 13, according to expression (1), is equal to zero U, R -, and M8 op R, p. The measurement interval is followed by the error correction interval. , and switch 15 and switch 24 are turned on after some delay t required for attenuation, transient process in the differentiating unit. In the correction interval, when the switch 15 is open, the voltage at the output of amplifier 13 is constant, therefore, the voltage at the output of amplifier 17 is equal zero and the output voltage is integral ruyuschego .usilitel 19 continuously and is determined from vfazheni Uit. +, (3) - voltage output of amplifier 19; -nominal resistors 18 and 22, «18 If we accept R | g Rj, then, + and„ 0. (4) When the switch 15 is closed, the output of the amplifier 13 is set to zero voltage, i.e. the voltage is changed by an amount equal to the initial value, taken with the opposite sign and iU ,, -and "and". K, g 14 This increment introduces the amplifier 7 into the limitation, which is in this state until the integrating amplifier 19j integrates the output voltage of the amplifier 17 and does not compensate for this change by its opposite, but opposite in sign, change in its output voltage. The change in the output voltage of the amplifier 19 on the one hand from the expression (5) is equal to UU ,, -uU ,, - and „п R ,, j С 4 On the other hand, this is increment, as a result of integrating the output interval T .. th the voltage is - / and, (t) dt. (7. And, - - But the output voltage of the amplifier I7 through the resistor 23 and the closed switch key 24 goes to the integrated amplifier of the first channel. Its output voltage also changes by the value of. And, - (t) dt, ( 8 2 0. Capacitance of the output integrator capacitor. Solving together the expressions (7) and (8), we get lU, p If the time constants and RJ, С „are equal, and in С, 4 take equal measurements T, then the output amplifier of the first channel, integrating on the error correction interval the output voltage of the amplifier 17, changes its voltage by the value of - ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––––– the output of the first channel becomes proportional to code X, recorded in the operative memory register at the first address, to the accuracy of which the listed time requirements are met. In the next measurement interval, the device measures the correspondence of the output voltage in the second channel of the code written tue rum at., and adjusts it to the range correction, etc. Similarly, all n channels are measured and corrected and then the cycle is repeated again. The error signal measured by the integrating amplifier is zero if in equation (l) the expression in brackets is zero. Then j. (X-iL t t -Uon. At zero error signal, the correction signal at the correction interval is equal to HyjDo, since the voltage at the output of amplifier 13 does not have a jump when shorting key 15. Therefore, the output voltage of the corrected channel remains unchanged. In order for the establishment of the output value to end in one correction interval, it is necessary that the increment of the output value from expression (9) correspond to the output value when zero in this case, the output value is set to with the input code in each channel for the first correction interval the accuracy with which a .vtoln last equality and equality r t R / a (J-4 and

Claims (2)

1. A multichannel digital-to-analog converter containing a source of reference voltages, the first and second outputs of which are connected to the corresponding information inputs of the first and second keys, the control input of which is connected to the outputs of the first and second elements, respectively, the first inputs of which are combined and connected to the first the output of the control unit, and the second inputs are connected respectively to the direct and inverse outputs of the trigger; the information input of the trigger is connected to the sign of the memory register, info The memory outputs of which are connected to the information inputs of the code converters in the time interval, the information inputs of the memory register are input buses, the second output of the control unit is connected to the synchronization input of the code converter in the time interval, the output of the clock generator is connected to the clock input of the code converter in the time interval, and the information outputs of the first and second keys are combined and connected to the first input of the integrator, the third key, characterized in that, in order to expand Functional capabilities due to multichannel information processing, a differentiating current-limiting element, two analog switches, an address counter and an integrating amplifier block, whose outputs are output buses and connected to the corresponding inputs of the first analog switch, whose output through the current-resistor is connected to the second, are introduced into it the integrator input, the output of which is connected to the information input of the third key and to the input of the differentiating unit, the output of which through the current-limiting element is connected to the information input of the second analog switch, whose information outputs are connected to the inputs of the integrating amplifier unit, and the address inputs are combined with the address inputs of the first analog switch and address inputs of the memory register and are connected to the outputs of the address counter, the input of which is combined with the clocking trigger input and Connected to the second output of the control unit, the third and fourth outputs of which are connected to the control inputs of the first and second analog switches, respectively, The INPUTS are connected to the outputs of the code converter in the time interval, and the fifth output is connected to the control input of the third key, the output of which is connected to the third input of the integrator. 2. The converter according to claim 1, which is characterized by the fact that the control unit is executed on three triggers. pax, the delay element and the one-shot standby, the output of which is connected to the S-input of the first trigger and is the third output of the block, the fourth output of which is the output of the first trigger, whose R-input is combined with the input of the delay element, with the input of the second trigger, connected to the output of the third trigger and is the second and fifth outputs of the block, the first output of which is the output of the second flip-flop, whose R-input and the C input of the first flip-flop are the first inputs of the block, the output of the support element is connected to the input of the waiting one-shot. Fi.Z