SU1659914A1 - Device for monitoring of operability of phased-array antenna with pin-diode phase-shifters - Google Patents

Abstract

The invention relates to monitoring means and can be used to monitor the health of a phased antenna array (PAIR). The purpose of the invention is to increase the reliability of the control. The device contains a current transformer 4, a time selector 5, a time converter 6 - a code, a power supply unit 7 for pin diodes 3 on which a phase shifter 2 is controlled by PARAM 1, a phase calculator 8, a health analyzer 9, an indicator 10, a synchronizer 11 and a absorbing unit 12 tension The health or malfunction of the pin diode 3 is judged by the tolerance control of the duration of the current pulse in the resorption voltage circuit. This makes it possible to determine the fault of the pin diode 3 not only of the open type, but also of the short circuit type, which increases the reliability of the control. 2 Il.

Description

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The invention relates to monitoring means and can be used to monitor the health of a phased antenna array (PAIR).

The purpose of the invention is to increase the reliability of the controls.

Figure 1 shows the structural electrical circuit of the device for monitoring the performance of HEADLIGHTS with phase shifters on pin diodes; Fig. 2 shows time and voltage diagrams in the device circuits.

A device for monitoring the operability of a phased antenna array 1 with phase shifters 2 on pin diodes 3 contains a current transformer 4, a time selector 5, a time converter 6 — a code, a pin diode power unit 7, an 8 phase calculator, a health analyzer 9, an indicator 10, a synchronizer 11, and a resorption stress block 12. The output of the power supply unit 7 is connected via a power bus to the phase shifters 2 PHAR1, and the output of the absorber voltage unit 12 to the phase shifters 2 via the primary winding of the current transformer 4. The first output of the calculator 8 phases is the output for connecting the control inputs of the controlled PAR1, and the second output is connected to the first input of the health analyzer 9. The first output of the synchronizer 11 is connected to the second input of the health analyzer 9, and the second output of the synchronizer 11 is connected to the control input of the calculator 8 phases and the first input of the time selector 5, the second input of which is connected to the secondary winding of the current transformer 4. The output of the time selector 5 is connected to the input of the time converter 6 — the code whose output is connected to the third input of the health analyzer 9. The output of the analyzer 9 health connected to the input of the indicator 10.

The device for monitoring the performance of the HEADLIGHT operates as follows.

In the Control mode, the calculator of 8 phases, using a special program, generates control signals arriving at the control inputs of the HEADLAMP 1 and providing alternate switching on and off of the checked pin diodes of the 3 Phase 1 phasers with the frequency of the control pulses of the synchronizer 11 (time diagram Ui (t) in figure 2, a).

When the checked discharge is switched on, the voltage of the positive bias is applied to the pin diode 3 and the current I 0 + lynp flows through the power supply bus from power supply 7, where 0 is the rest current of HEADLAMP; control is the control current of the checked discharge (pin diode 3).

The passage of a ctr current through a pin diode introduces it into saturation mode, creating a Unas voltage drop across it (time diagram U2 (t) in Fig. 2b, section 2). At the same time, a rather significant electric charge Q pin accumulates on the pin diode, amounting to a few tens to hundreds of nanocolons,

The time for switching the pin diode from an open state to a closed state is determined by the resorption time of the accumulated charge Q pin. When the checked pin diode of the phase shifter is turned off, the negative polarity voltage from the dissipation voltage unit 12 is fed through the primary winding of the current transformer 4 to the corresponding pin diode (time diagram U2 (t) in Fig.2, b, sections 1 and 3) , providing accelerated resorption of charge Qpin. At the same time, a resistive voltage bus (primary winding of current transformer 4) from the positive electrode of the pin diode to the resorption voltage unit begins to flow a discharge current, causing an exponential current pulse with a current duration in the secondary circuit of the transformer 4 (time diagram i (t) Fig.2, c), determined by the resorption time of the electric charge Qpin. This pulse in the time selector 6 is extracted and transformed into a rectangular pulse of a logic level voltage (time diagram Ua (t) in Fig. 2, d), the duration of which, proportional to the accumulated electric charge Qpin, characterizes the performance of the tested bit (pin diode 3) phase shifter 2 FAR1.

If the tested discharge of phase shifter 2 consists of several pin-diodes connected in parallel, the magnitude of the decrease in duration at the output of the time selector will determine the number of diodes that have failed in the form of a break. In the event of a failure involving the interruption of all the diodes of the tested discharge, or a short circuit of one of the diodes of the phase shifter, the accumulated charge Qpin 0 and the pulse at the output of the time selector 6 will be absent.

The duration of the output pulse of the time selector 5 with the help of the time converter 6 is the code converted into a parallel digital code that is fed to the health analyzer 9, where its tolerance control is carried out. At the same time, the code of the sequence number of the controlled phase shifter from the calculator 8 arrives at the health analyzer 9.

phases and sync pulse from synchronizer 11.

8 case, if the controlled duration of the absorption time of the charge Qpln is outside the tolerance, in the analyzer

9, a fault pulse is generated, which is the resolution for passing on its output the code of the sequence number of the phase switch to be checked (failed).

From the output of the analyzer 9, the code of the number of the failed phase shifter enters the indicator 10, where it is recorded, stored until subsequent zeroing and indication.

Thus, the proposed device allows detecting failures without an increase in hardware costs, which are caused not only by the break, but also by the short-circuiting of the pin diodes of the 3 PHAR1 phase shifters, which significantly (approximately two times) increases the reliability of monitoring the efficiency of the HEADLAMP compared to the prototype.

Claims (1)

Invention Formula Device for monitoring the performance of a phased antenna array with U Plot 1 Plot 2 Plot pin phase shifters, including a health analyzer, the output of which is connected to the indicator input, a phase calculator, the first output of which is the output for connecting the control inputs of the monitored phased antenna array (PAR), and the second output of the phase calculator is connected to the first input of the health analyzer, the synchronizer, the first output of which is connected to the second input of the health analyzer, and the second output - to the control input of the phase calculator , a current transformer and a power bus, distinguished by the fact that, in order to increase the reliability of the control, a series-connected time selector and a time-code converter were introduced. the output of which is connected to the third input of the health analyzer, the first input of the time selector is connected to the second output of the synchronizer, and the second input of the time selector is connected to the secondary winding the current transformer, the primary winding of which is the resorption voltage busbar of the pin diodes of phase shifters controlled by the HEADLAMP. Rig.2