SU1659887A1 - Device for tolerance monitoring voltage - Google Patents

Abstract

The invention relates to a pulse technique and can be used to control a voltage in a given range. The purpose of the invention is to expand the functional input due to the fact that, due to the independence of the lower and upper response thresholds from the change in the reference voltage, the device can be used to control the amplitude of the signal "MOS circuits at different supply voltages without setting additional threshold levels" the second source 6 of the reference voltage and the operational amplifier 7. The device also contains a complementary MOS transistor inverter 1, a resistor 2, the first source 3 reference voltage, indicator 4, threshold element (comparator) 5. 2 Il. w y os ate about 00 00 VI

Description

The invention relates to a pulse technique and electrical measurements and can be used to monitor voltage in a given range, in particular to control the amplitude of logic levels of CMOS circuits.

The purpose of the invention is to expand the functionality of the device due to the fact that, due to the independence of the values of the lower and upper response thresholds from changes in the reference voltage, the device can be used to control the amplitude of the CMOS signal at different power voltages without setting threshold levels.

FIG. 1 shows a functional diagram of the device; in fig. 2 - time diagrams of his work.

The device contains a complementary MOSFET inverter 1, a resistor 2, a first voltage source 3, an indicator 4, a threshold element (comparator) 5, a second voltage source 6 and an operational amplifier 7. The input of a complementary MOS transistor inverter 1 is input device and connected to the gates of the first and second MOS transistors 8 and 9, the drains of which are combined, the drain of the first MOS transistor 8 and the substrate are connected to the inverse input of the operational amplifier 7 and through a resistor 2 to the output of the operational wisi The telephone 7 and the first input of the threshold element 5, the drain of the second MOS transistor 9 and the substrate are connected to the common bus, the direct input of the operational amplifier 7 is connected to the source 6 of the reference voltage, and the second input of the threshold element 5 is connected to the source 3 of the reference voltage , the output of the threshold element 5 is connected to the indicator 4 and to the output bus.

The device works as follows.

The inverter 1 MOSFET transistors operate in the mode of controlled resistors. At the output of the operational amplifier 7, a voltage UA is set to

UA-UR + UI,

where UR is the voltage drop across resistor 2;

Ui is the voltage of the reference source 6.

The voltage source 3 sets the voltage IJ2. which is within the boundaries

 idmax

where idmax is the voltage at the output of the opamp 7 at the maximum current flowing through the resistor 2.

When the input signal is zero (Fig. 2), the second MOS transistor 9 of the inverter 1 is closed and the first MOS transistor 8 is open. No current flows through resistor 2

and The output of the operational amplifier 7 at the same voltage. The threshold element 5 compares the voltages U2 and UA, since UA U2, then the output of the threshold element 5 is high

0 logic level and indicator 4 is turned off, which indicates that the input signal level is below the lower Unu threshold level (figure 2).

When increasing the input voltage

5 of the signal of the second MOSFET 9 of the inverter 1 opens and current flows through the resistor 2, the output voltage of the operational amplifier 7 UA increases and if it reaches or exceeds the voltage U2 (Fig. 2), the threshold element 5 changes its state and at its output, a low logic level is turned on, switching off the indicator 4 and indicating that the input signal level is equal to

5 or above the lower threshold level 1) well, but below the upper threshold level UBy (Fig. 2). With a further increase in the input signal due to the change in the ratio of the resistance of the channels of transistors 8 and 9

0, the current flowing through the resistor 2 reaches a maximum and then decreases. The voltage .UA also reaches a maximum of idmax and then decreases. And, if at the same time it will be lower than 1) 2, then the output

The 5th threshold element 5 is set to a high logic level too, the indicator 4 is turned on, which indicates that the input signal level has exceeded the upper threshold level.

0 When the voltage U2 of the source 3 of the reference voltage is changed symmetrically to the relative common bus and relative to the voltage Ui given by the source of the reference voltage, the lower Unu and the upper 1) threshold levels change accordingly from 5. A change in the reference voltage of source 6, for example, an increase from Ui to Ui (Fig. 2), changes the upper threshold value by the same amount.

0 level, which is equal to uSy-U ey-KUi-Ui)

The symmetry of the response thresholds not only allows monitoring the voltage within acceptable limits, but also controls the amplitude of low and high levels of logic signals, such as CMOS circuits, whose high level relative to the power bus is comparable to a low level.

Claims (1)

Invention Formula A voltage tolerance control device containing a complementary MOS transistor inverter, including the first and second MOS transistors, whose drains are connected to the substrate, the sources are combined, and the gates are connected to the input bus, a resistor connected to the first input of the threshold element, the first source of reference voltage connected to the second input of the threshold element, the output of which is connected to indie With an output busbar, characterized in that, in order to expand its functionality, a second voltage source and an operational amplifier, the inverse input of which is connected to the second output of the resistor and to the drain of the first MOS transistor, are entered into it, the direct input is connected to the second source of the reference voltage, and the output to the first output of the resistor, while the drain of the second MOS transistor is connected to the common bus, and a comparator is used as the threshold element. uk Mon  // IWU 6x 2