SU1658181A1 - Logic image processor - Google Patents

Abstract

The invention relates to automation and computing, and is intended to construct matrix processes. The purpose of the invention is to increase the speed of the device. The device contains a matrix of optical transducers, each of which consists of identical cells having three bispin elements, two optoelectronic gates, two light emitters, and three resistors. Due to the matrix organization and multi-channel, not only high speed is provided, but also the flexibility of the device is functional. 1 hp f-ly, 2 ill.

Description

The invention relates to automation and computing and can be used in various optoelectronic parallel image processing circuits, in constructing matrix processes for calculating the logical functions of binary images using cellular logic methods.

The aim of the invention is to increase the speed of the device.

FIG. 1 shows the general structural scheme of the device, schematically disclosed the implementation of the optical converter device; FIG. 2 shows time diagrams of supplying control signals to the device inputs explaining the essence of its operation.

The device contains a matrix of 1 (mxn) optical converters, the optical inputs and outputs of which form, respectively, external optical information input 2 and output 3 of the device, each matrix cell contains the first 4, second 5 and third 6 bis-elements, whose ohmic power leads are connected to the bus 7 powering, locking the output of the first bispan device 4 is connected to the first electrode of the first optoelectronic gate 8 and through the zero busbar mogut resistor; the second electrode of the first optoelectronic gate is connected to the first control unit the auxiliary electrical input of the cell, the optical input of the first bispin element 4 is connected to the optical input of the cell, the contact of the substrate of the first bispin element remains free, the optical input of the first optoelectronic gate 8 is connected to the first control optical input of the cell, and its optical output is connected to the optical input of the second bispan-element 5, the contact of the substrate of which is connected to the second electrical input of the cell, and the locking contact is connected to the first electrical terminals of the first light emitter (light odioda) 9 and an insulating optoelectronics second shutter 10, the second terminal of the light emitter 9 via a load resistor and a second terminal connected to the optoelectronic shutter 10 with a zero bus, an optical output coupled to the light emitter 9 opticheso

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The primary input of the second bispin element 5, the optical input of the second optoelectronic shutter 10 is connected to the second control optical input of the cell, and the optical output of the second optoelectronic shutter 10 is connected to the optical input of the third bispin element 6, the substrate contact of which is connected to the third control electrical input of this cell, the closing contact is with the first electrical output of the second light radiator 11. A second electrical output of which is connected to the zero bus through a load resistor, and the optical output is The first LED is connected to the optical input of the third bispin-element 6 and the optical output 3 of this cell, all the first, second and third electrical inputs of each cell of the matrix are connected together together and form the first 12, second 13 and third 14 electrical inputs of the device, the first and second optical the inputs of each cell of the matrix are connected respectively to the first 15 and second 16 optical control inputs of the device.

FIG. Figure 2 shows the timing diagrams of the supply of control signals to the control inputs 12-16, as well as to the optical input 2 of the device.

The device works as follows. . The computed logical function f (XiXp) of the input images is formed according to the rule f VTj, where: Tj XL .. XkXk + i ... Yj, the j-th image term composed of the product of direct X or inverse X images; YJ is the adjustment image of the resolution of the j-ro term in this logical operation.

Each H term is formed according to the rule.

Tj Xi ... XkXk-n ... XnYj Xi Xk + Yj + Xic-n ...

Thus, by supplying the input optical signals of the current images X to the optical inputs 2 of the optical converters of the array, which coincide with the optical inputs of the first bipinn-samples 4 at the locking contact, and consequently, at the first electrode of the first optoelectronic gate 8, the power supply voltage If the optical input 2 receives a single signal.

If the input 12 has a voltage and an optical signal is present via the optical input 2, then the resistance of the first bispin-element 4 drops, and the value of the first resistor limiter is selected so that the power at the top electrode of the gate 8 equals the power of the control input 12. In this a case of parallel luminous flux from the input 15. If there is no input 12

an optical signal, then the potential difference between the electrodes of the gate 8 is sufficient for the gate 8 being closed. Therefore, if there is power at the input 12, then the first cell circuit is used as an optical repeater. Similarly, if there is no power at input 12, then this circuit is used as an optical inverter. In fact, this cut (first bispin-element 4 and

0 gate 8) in all cells of the array is an optical repeater-inverter with a signal optical input 15 and control optical 2 and electric 12 inputs.

5 The second bispin element 5 of each cell, due to the presence of optical feedback from the LED 9, serves to accumulate the array of the device. The inversion of the logical sum of the direct and inverse images and the adjusting image into the logical product of the corresponding inverse images (term) is reached at the output of the second gate 10, since if the top electrode of this gate had a potential 1 formed by disjoint the optical signals of the current operands ( light, tuning and inverse), then the light signal from the input 16 from the source of the plane-parallel light

0, the flow does not pass through this gate, and vice versa, if there is no power supply on the upper electrode of the second gate, this gate becomes transparent for the optical signal from the source 16 to pass.

5 The third bispan-element 6, due to the reverse optical communication of the LED 11, generates a logical sum of the values of the generated terms. After all terms are formed, the result of reading at the optical output of the second LED 11, but in the process of forming from the output of this LED, it is possible to read intermediate results, the formation of which does not require the values of all possible terms, no further processing is affected.

A reset of the second 5 and third 6 bis-elements is necessary, respectively, for

0 forming the value of a new term or a new logical function. This is achieved by supplying the appropriate control signals to the control inputs 13 and 14 of the device, as shown in FIG. 2 (the sequence of formation and coordination of these signals in time).

FIG. Figure 2 shows timing diagrams for the formation of four image terms for two operands X and Xg for each of the device inputs. Similarly

term formation is performed for a larger number of information operands.

Claims (2)

1. A device for logical processing of 5 images containing a matrix of optical converters, the information inputs of the optical converters of the first column of the matrix and the outputs of the optical converters of the last column of the matrix are respectively the information inputs and outputs of the device. characterized in that, in order to increase speed, the information inputs of each optical converter of each line are optically connected with the outputs of the previous optical converter of the same row of the matrix, three like electrical control inputs of all optical converters 20 are combined and are electric the device inputs, the two optical optical control inputs of the same name of all optical converters are combined and are the optical control inputs of the device, The respective power inputs of the optical inputs of all optical converters are connected and are the power inputs and the information input of the device. 2. The device according to claim 1, characterized in that each cell of the converter consists of three bispin elements, two light emitters, three resistors and two opto-electronic gates, with the optical 35 inputs of the first bispin elements being the information inputs of the optical converter, the first electrical inputs of the first optoelectronic converters and the electrical inputs of the second and third bipinn elements are the electrical control inputs of the optical converter, the optical inputs of the optoelectronic switches are the optical control inputs of the optical converter, the outputs of the first bispin elements are connected to the second the electrical inputs of the first optoelectronic converters and the first terminals of the first resistors, the outputs of the first and the second optoelectronic gates are optically coupled to the optical inputs of the second and third bispin elements, respectively, the outputs of which are connected to the first inputs of the first and second light emitters, respectively, the second inputs of which are connected to the first terminals of the second and third resistors, the second electric inputs of the second optoelectronic gates are connected to the first inputs of the first light emitters, the power inputs of the bispan-elements are interconnected and are the power inputs of the optical converter; the second terminals are the resist trench and are united by common vhodag mi optical pickup outputs of the first and second light emitters are optically coupled with optical inputs respectively of the second and third bispin elements, and outputs the second radiator are also outputs of the optical pickup SPT SPT SPT SPT SPT SPT 1