SU1656691A1 - Autocorrelation receiver of signals with two-fold differential phase shift modulation - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to improve noise immunity. The autocorrelation receiver contains an adjustable phase shifter 1, a storage unit 2, multipliers 3 and 4 functions, a phase shifter 5, integrators 6 and 7, keys 8, 9, 14 and 22, comparators 10, 13 and 21, elements 11 and 12, elements OR 15, 18 and 23, drives 16 and 19. differential amplifier 17, inverter 20 and driver 24 pulses. This receiver generates an error signal that controls the operation of the adjustable phase shifter 1, which compensates for the phase shift that occurs between the voltages supplied to the multipliers 3 and 4. This reduces the noise immunity due to the effect of carrier instability. 2 Il.

Description

The invention relates to communication technology and can be used in data transmission systems.

The purpose of the invention is to improve noise immunity.

FIG. Figure 1 shows the structural scheme of the proposed autocorrelation receiver: FIG. 2 is a storage scheme.

The autocorrelation receiver contains an adjustable phase shifter 1, a storage unit 2, the first multiplier of 3 functions, the second multiplier of 4 functions, the phase shifter 5, the first, the second integrator 6, 7, the first key 8, the third key 9, the first comparator 10 the first element 11 and the second element AND 12, second comparator 13, second key 14, second element OR 15, first drive 16. differential amplifier 17, third element OR 18, second drive 19, inverter 20, third comparator 21, fourth key 22, first element

OR 23, shaper 24 pulses. The drive 16 contains a ring register 25, integrators 26, keys 27, an adder 28, a divider 29 on p.

The autocorrelation receiver operates as follows.

The signal goes to multiplier 3 and through phase shifter 5, providing phase shift by W / 2, to multiplier 4. To other inputs of multipliers 3 and 4, the input signal goes through adjustable phase shifter 1 and storage unit 2, which stores information about the previous message. An adjustable phase shifter 1 provides a constant value of the phase shift of the signal at the output of the storage unit 2 with respect to the input signal by / 4.

After multiplication and integration, the binary signals transmitted to the channel are formed at the outputs of the integrators 6 and 7:

Ui-EcCi1-Eccos (-Dr | -1 + J);

(L

WITH

oh oh oh u

U - ECC, 1 - Eccos (Api - Beam - 1 -).

In the event of a phase shift between the voltages supplied to the multipliers 3, 4, e.g., UI ± 15 °, the Ci values change. Ci values are given in the table,

In the prototype, a control signal to compensate for the phase shift to the input of the variable phase shifter is supplied only with combination 1. The proposed receiver suggests using combination 3 (see table). It happens as follows. The outputs of the integrators 6 and 7 are connected to the inputs of comparators 10 and 13 and the inputs of keys 8 and 14. Keys 8 and 14 are opened under the action of a control signal produced by element 11, the inputs of which receive signals of a logical unit only when the voltage on the inputs Comparators 10 and 13 have a positive sign, which is the case with a combination of 1 (see table). The outputs of the keys 8 and 14 are connected through the corresponding elements OR 15 and 18 to the inputs of the accumulators 16 and 19. If the voltage at the output of the integrator 7 is negative, at the output of the integrator 6 is positive, as is the case with combination 3 (see table), the keys are opened 9 and 22. The control signal to them in this case comes from the output of the element And 12. The inputs of the element And 12 receive the signals of the logical unit from the output of the comparator 10 and the comparator 21. The negative voltage from the output of the integrator 7 is converted into positive in the inverter 20. so in this beam on the positive input of the comparator 21 signal is applied. Through the public key 9, the signal from the output of the integrator 6 through the element OR 18 is fed to the input of the accumulator 19, and the signal from the output of the integrator 7 through the inverter, the public key 22 and the element OR 15 is fed to the input of the storage 16.

Drives 16 and 19 average the signal from the integrator outputs.

At the moment the device is turned on for the first bit of the ring register 25, a logic unit signal is recorded. When a positive signal arrives at the outputs of either the element 11 or element 12 that are combined in the element 23, the pulse generator 24 is started. The signal from the output of the generator 24 transfers the logical unit recorded in one of the bits of the circular register 25 the next bit of the same register is 25. The signal from the bit output of the ring register 25, where the logical unit, for example the second, is entered, resets the corresponding integrator 262 and opens the corresponding key 272, through which the signal from the element output and OR 1 ° is input to the integrator 262. Thus,

after a time equal to the duration of the p elements, in the integrators 26 the values of the n signals will accumulate, which are then summed up in the adder 28 and averaged in the divider 29 by

0 p. The outputs of the accumulators 16 and 19 are connected to the inputs of the differential amplifier 17, at the output of which an error signal is generated that controls the operation of the adjustable phase shifter 1, which compensates

Claims (1)

5, the phase shift arising between the voltages supplied to the multipliers 3 and 4 functions and, thus, eliminating the reduction of noise immunity. Invention Formula 0 An autocorrelation receiver of signals with a double phase difference modulation containing a series-connected adjustable phase shifter and a storage unit whose output is connected to the first inputs of the first and second function multipliers; the second input of the second function multiplier is connected to the output-phase switch, which is connected to the input of the second function multiplier the phase inverter and the first input of the first multiplier of functions, is the input of the autocorrelation receiver, the output of the first multiplier of the function is connected with the input of the first integrator, the output of which is connected to the input of the first key and the first comparator, the output of which is connected to the first input of the first element AND, the output of the second function multiplier is connected to the input of the second integrator, the output of which is connected to the input of the second key and the second comparator, output which is connected to the control inputs of the first and second keys, the differential 5 an amplifier whose output is connected to a control input of an adjustable phase shifter, characterized in that, in order to improve noise immunity, an inverter, a third comparator, 0 second element AND, three elements OR, third and fourth key, pulse shaper, first and second drives, while the output of the second integrator is connected via an inverter to the input of the third computer, the output of which is connected to the first input of the second element AND, the second input is connected with the output of the first comparator, and the output to the first input of the first element OR and the control inputs of the third and fourth keys, the output of the fourth key is connected to the first input of the second element OR, the second input of which is connected to the output of the first key, and the output to the input of the first accumulator, the output of which is connected to the first input of the differential amplifier, the output of the third key is connected to the first input of the third OR element, the second input of which is connected to the output of the second key, and the output to the input of the second accumulator pod0 The key is connected to the second input of the differential amplifier, the second input of the first element OR is connected to the output of the first element I, and the output to the input of the pulse former, the output of which is connected to the synchronous inputs of the first and second drives, the output of the inverter is connected to the input of the fourth key connected to the input of the third key. 28