SU1656683A1 - Integral digital-to-analog converter - Google Patents

Abstract

The invention relates to automation and can be used in digital-to-analog data conversion systems. The purpose of the invention is to increase the reliability of converting a code to an analog signal while maintaining the range of variation of the reference voltage. The integrated digital-to-analog converter contains 2 series-connected resistors 1.11; 2n, 2m keys in each category made in two groups of MOS transistors with N-type conduction channels, where m is the number of the discharge and PL n, (n-1) 2, 1 and an additional MOSFET channel P-type conduction. A positive effect is achieved due to the introduction of an additional P-type MOS transistor and the implementation of the first discharge MOS transistors of both groups with equal threshold voltages. 1 il.

Description

The invention relates to automation and can be used in systems for converting digital information to analog.

The purpose of the invention is to increase the reliability of the conversion of the code into an analog signal while maintaining the range of the reference voltage.

The drawing shows a functional diagram of an integrated digital-to-analog converter.

The integrated digital-to-analog converter contains 2 ^P series-connected resistors 1.1.1.2 ..... 1.2 ⁿ , 2 ^{tons of} keys in each category, made in two groups of 2 and 3 MOS transistors with an N-type channel, where m is the number of the discharge and m = n, (n-1) ..... 2.1, and an additional MOS transistor 4 with a P-type channel.

Integrated digital-to-analog Converter operates as follows.

The reference voltage Uon (for example, 2.5 V) is supplied to the input voltage reference bus, and a convertible code is supplied to the direct and inverse control buses. Depending on the value of the converted code, the corresponding transistors of the first 2 and second 3 groups turn on and off. As a result, a connection is established between a specific node connecting resistors 1 (from 2 ^P series-connected resistors) through the included MOS transistors with the output bus. MOS transistors of the first group 2 and an additional MOS transistor 4 switch voltages from Uon to Uon / 2, and MOS transistors of the second group 3 switch voltages from Uon / 2 to 0. In this case, a voltage proportional to the value of the converted code is generated on the output bus of the integrated digital-to-analog converter .

Large switching voltages of the first group of 2 MOS transistors increase (due to the substrate effect) the effective threshold voltage of these MOS transistors. To compensate for the increase in the threshold voltage, the MOSFETs of the first group 2 have a threshold voltage of (0.2-0.6) V lower than in the MOSFETs of the second group 3. Due to the difference in the threshold voltages of the MOSFETs of the first 2 and second 3 groups, the alignment operating conditions of MOS transistors of both groups. In this case, the resistance of the switched on MOSFETs of the first group 2 approaches the resistance of the switched on MOSFETs of the second group 3.

The initial level of the threshold voltage of the MOSFETs of the first group 2 and especially the MOSFET in the first (senior) category determines the margin for a possible decrease in the threshold voltage when environmental conditions change during the operation of the digital-to-analog converter. Moreover, in the case of switching voltages close to zero, the switching properties of the MOS transistors are limited by leakage currents due to the low effective threshold voltage and low reverse bias voltage of the source of the MOS transistor relative to the substrate. This leads to a deterioration in the reliability of the conversion results (lower reliability).

The introduction of an additional MOS transistor 4 with a channel of P-type conductivity in the key of the first category eliminates the need to have a low threshold voltage for switching voltages approaching the value of Uon. Due to this, the difference in the initial values of the threshold voltages of the MOSFETs of the first 2 and second 3 groups can be reduced and the level of the initial threshold voltage increased to 0.8-1.2 V. To maintain the range of variation of the Uon level, the total resistance of the included MOSFETs of the first group the first discharge and the additional MOSFET 4 should not exceed the resistance of the included MOSFET of the second group of the first discharge. When this condition is met, the time constant of the digital-to-analog converter on the output bus does not impose restrictions on its speed.

Claims (2)

Claim An integrated digital-to-analog converter containing an input reference voltage bus and a zero potential bus, between which 2 ^P series-connected resistors and discharge keys are included, 2 ^{tons of} keys in each category, made on two groups of 2 ^ ^t (n-1), k. .... 1, with channels (hl = 1) N-type conductivity, the drains of the corresponding 2 ^ '^ MOSFETs of the first and 2' ⁿ MOSFETs of the second groups of the ηth category are connected to the second terminals of the corresponding resistors from 2 ^P series-connected resistors, 2 MOSFET transistors of the second groups of the k-th category are connected to the corresponding combined sources of J-ro and O + LUGO MOS transistors of the first and second groups of the (k + 1) -th category, respectively. where k = (n ~ 1), (n-2) ..... 1. j = 1.3.5 ..... (2 ^k_1 -1), the source of the MOS transistor of the first group of the first discharge is combined with the source of the MOS transistor of the second group of the first 10 discharge and is the output bus, the gates Jx of the MOS transistors of the first and second groups of the corresponding discharge , except for the first one, the gates of the 0+ 1) MOS transistors of the first and second groups of the corresponding discharge are combined and are the direct control bus of the corresponding discharge, except the first one, the gates of the MOSFETs of the first and second groups are combined and are the inverse control bus of the corresponding category of the first category are direct and inverse control buses of the first category, respectively, the MOS transistors of the first group of each category, except for the first 25, are made with threshold voltages of the corresponding storages of the first and 2 ' ^to ' ¹ voltage lower than the threshold voltages of the MOS transistors of the second group of each discharge, characterized in that, in order to increase the reliability of the result of converting the code into an analog signal while maintaining the range of the reference voltage, an additional MOS transistor is introduced into it, connected to the channel of the P-type conductivity, the drain and source of which are combined respectively with the drain and source of the MOS transistor of the first group of the first discharge, the gate of the additional MOS transistor is combined with the gate of the MOSFET of the transistor of the second group of the first discharge, the open channel resistance of the additional MOS transistor selected in accordance with the ratio Ri R2 20 ^extra ~ Ri - R ₂ 'where Rflon is the open channel resistance of the additional MOS transistor; Ri. ₽2 - the resistance of the open channels of MOSFETs of the first category, respectively, of the first and second groups of MOSFETs.