SU1647868A1 - Logic signal driver for on/off power supply control - Google Patents

Abstract

The invention relates to a pulse technique and can be used to form a timing diagram for the initial startup and shutdown of the processors. The purpose of the invention is to simplify the driver — by changing the principle of forming the output timing diagram. Shaper logic signals on the on-off voltage supply contains the element AND NOT 1, Comparators 2 3.34, transistors 4, 5, diodes 6-8 and 35-37, capacitors 9-11, resistors 12, 14 22 and 26 - 33, common power bus 13, positive power supply bus 23, logic outputs 24, 25, element OR-NOT 38, power control input 39, mains voltage control input 40, shaper supply voltage control input 41, positive bus 42 power supply, restart input 43, power supply voltage control input 44. By introducing the comparator 34, the diodes 35,36,37, the element OR-38 and the new connections, the elimination of a larger number of logic elements is provided, which simplifies the driver. 1 il. WITH

Description

The invention relates to a pulse technique and can be used to form a timing diagram of the initial start and shutdown of processors, for example, series K581, K1801.

The purpose of the invention is the simplification of the shaper by changing the principle of formation of the output time diagram.

The drawing shows a diagram of the shaper,

The shaper contains an INE 1 element, the first 2 and second 3 comparators, the first 4 and second 5 transistors, the first 6, the third 7 and the second 8 diodes, the first 9, the second 10 and the third 11 capacitors, the seventeenth resistor 12, the common bus 13, the first resistor 14 the third resistor 15, the second resistor 16, the fifteenth 17 and the fourteenth 18 resistors, the sixteenth 19. the thirteenth 20, the sixth 21 and the fourth 22 resistors, the positive bus 23 of the power supply, the second 24 and the first 25 outputs, the fifth 26, the seventh 27, the twelfth 28 , eighth 29, ninth 30, tenth 31, eleventh 32 ,. eighteenth 33 resistors, the third comparator 34, the sixth 35, the fifth 36 and the fourth 37 diodes, the element OR NOT 38, the second 39, the third 40, the fourth 41 inputs, the positive power bus 42, the fifth 43 and the first 44 inputs, the third output 45.

The first comparator 2 is connected by an inverting input to the first terminals of the first 14, second 16 resistors and the first capacitor 9, a non-inverting input with the first terminal of the third resistor 15, the first diode 6 is connected by a cathode to the second terminal of the second resistor 16. Element And _; NOT 1 is connected by the first input to the first input 44 of the shaper, the first output 25 of which is connected to the first output of the fourth resistor 22 and the collector of the first transistor 4, connected by a base to the first output of the fifth resistor 26. The second transistor 5 is connected by a collector to the second output 24 of the shaper and the first output the sixth resistor 21, the base with the first output of the seventh resistor 27. The second comparator 3 is connected by an inverse input to the first terminals of the eighth 29 and ninth 30 resistors. The tenth resistor 31 is connected by the first terminal to the non-inverting input of the second comparator 3 and the first terminal of the eleventh resistor 32. The twelfth 28 and thirteenth 20 resistors are connected by the first terminals. The fourteenth resistor 18 is connected by the first terminal to the anode of the second diode 8, the second terminal is connected to the first terminals of the fifteen of the resistor 17 and the second capacitor 10.

The first 39, second 40 and third 41 inputs of the OR-NOT 38 element are, respectively, the second, third and fourth inputs of the driver, and the output is connected through the fourth 37 and third 7 diodes, respectively, with the second terminals of the eighth 29 and ninth 30 resistors, and directly with the second input of the AND-NOT 1 element, the third input of which is the fifth input 43 of the driver, and the output is connected to the anodes of the first 6 and fifth 36 diodes, with the cathodes of the sixth 35 and second 8 diodes. The anode of the sixth diode 35 is connected to the second terminal of the first resistor 14, the cathode of the fifth diode 36 is connected to the second terminal of the fifteenth resistor 17, the first terminal of the third capacitor 11 is connected to the inverting input of the second comparator 3 connected by the first output to the third output 45 of the former and the second conclusions of the eleventh 32 and the eighteenth 33 resistors. The second output of the seventeenth resistor 12 is connected to the direct input of the second comparator 3, the inverting input of the third comparator 34 is connected to the first output of the second capacitor 10, its direct input and first output, respectively, are connected to the second and first output of the twelfth resistor 28, the second output to the base the second transistor 5. The first output of the first comparator 2 is connected to the second terminals of the third 15. sixteenth of 19 resistors, the second output to the base of the first transistor 4.

Comparators 2,3 and 34 can be performed on standard integrated circuits of the K521CAZ type, the AND-NOT element and the OR-NOT element on standard K561 series microcircuits.

Shaper of logical signals for turning on / off the supply voltage works as follows.

When applying the mains voltage by switching on the toggle switch (not shown) to the network in the power source (not shown) of the power supply to the logic signal shaper, an auxiliary constant voltage (15 V) is supplied to the plus power line 42 and the common power line 13 of the former. Until the moment the switch is turned on (not shown), the logic unit level is input to the power-on control input 39. Input 40 monitoring the mains voltage, if the mains voltage is normal, receives a logic zero level. To the input 41 of the voltage control of the shaper, if the auxiliary constant

1547868 supply voltage (15 V) is normal, a logic zero level is received.

At the input 43 of the restart, since the restart switch is not turned on, the level of the logical unit is received. Input 44 controls the voltage of the power source receives a logic level of zero, since the voltage of the power source has not yet been established. Since the logical unit level is input to the input of the OR-NOT 38 element from the input 39 of the power-on control, it holds the output of the OR-NOT 38 element. the state of logical zero, while this level through the diode 7 and the resistor 30 is fed to the inverting input of the comparator 3, the output of which is set to the state of the logical unit using the load resistor 33. This indicates that from the input 39 of the power-on control there was no permission to turning on the power source and the operation of its power transistors (not shown) is prohibited. The levels of logical zeros entering the inputs of the AND-NOT element from the input 43 and the output of the OR-NOT 38 element. The output of the AND-NOT 1 element is held in the state of a logical unit, while the capacitor 9 is charged through the diode 6 and resistor 16, and through the diode 36 and the resistor 17 is a capacitor 10. The voltage levels of the charged capacitors 9 and 10, arriving, respectively, at the inverting inputs of the comparators 2 and 34, set their outputs to logical zero states, which, acting respectively on the bases of transistors 4 and 5, open them, and on you / moves 24, 25 of the former shaper dull logical zero levels. After turning on the toggle switch, the logic zero control input 39 receives a logic zero level and then to the corresponding input of the OR-NOT 38 element, the logic logic zero levels are already set at its other inputs (if the mains voltage and auxiliary DC voltage (15 V) are normal) . At the same time, the state of the logical unit is established at the output of the OR-NOT 38 element, and through the diodes 37 and resistor 29, the capacitor 11 is quickly charged (resistor 29 is selected so that its resistance value is negligible). When the voltage level at the capacitor 11 reaches the threshold voltage of the comparator 3, which is set by a voltage divider consisting of resistors 12 and 31, the comparator 3 is activated and a zero level signal is generated at its output, which is fed to the control output 45 of the power transistors of the power source.

The resistor 32 is turned on to eliminate the false triggering of the comparator 3 when the signal is bounce at its inverting input and sets some hysteresis for the triggering of the comparator 3. This signal allows the operation of the power source, which begins to form its output voltage. When these voltages reach the levels corresponding to the norm, the level of the logical unit starts to enter the input 44 of the voltage control of the power source, i.e. all inputs of the AND-NOT 1 element contain logical units. The output of the AND-NOT 1 element is set to zero, and the discharge of the capacitor 9 through the resistor 14 and the diode 35 and the discharge of the capacitor 10 through the resistor 18 and the diode 8 will begin. When the voltage across the capacitors 9 and 10 drops below the threshold level set, respectively, resistors 15 and 19, resistors 28, 20, at the outputs of the comparators 2, 34, logical unit levels are generated that enter the bases of transistors 4 and 5 and close them. At the same time, at the outputs and 25 of the shaper, levels of a logical unit are generated. The discharge time of capacitors 9 and 10 is set by setting the capacitance values of the capacitors themselves and the resistance values of resistors 14 and 18 (for processors of the K581 and K1801 series, this time is 3 ms minimum until a signal appears on the output of the driver from the moment the normal voltage of the power source and 73 ms at least until the appearance of the signal at the output 24 of the shaper). When the mains voltage decreases, when the power source is turned off, and the power supply voltage of the driver is lowered, the control signals of which are fed to the power-on control input 39, the mains voltage control input 40 and the driver voltage control input 41, the following occurs. When any of these signals appears as a single level at one of the inputs of the OR-NOT 38 element, a zero level is generated at its output, which closes the AND-NOT 1 element, setting its output to a single state. In this case, the capacitors 9 and 10 are charged, as described previously. When the voltage at the inverting inputs of the comparators 2 and 34 rises above the threshold level of their operation, logical zero levels will appear at their outputs, which go to the bases of transistors 4 and 5 and open them. At the same time, logic zero levels are supplied to outputs 24 and 25 of the logical signals of the former (for processors of the K581 and K1801 series, these times will be: 7 ms minimum for output 25 and 3 ms for output 24 of the former from the moment of power failure). After 5 ms, at least after removing a single level from the output 25 of the shaper, a single signal level is fed to the output 45 of the power transistor control of the power source. The removal of the enable signal of the power transistors of the power source is carried out. After removing the signals at the outputs 24 and 25 of the logic signals of the shaper as described above, i.e. when the output of the OR-HE 38 element is set to zero, the capacitor 11 is discharged through the resistor 30 and the diode 7, When the voltage on it drops below the threshold level of the comparator 3, the logic level appears at the output 45 of the power transistors of the power supply and then the unit turns off specified transistors. In the event that a decrease in any of the voltages of the power supply occurs, a logic zero level will be input to the voltage control input 44 of the power supply. The formation of the logic signals of the driver occurs in the same way, while the signal at the output 45 of the control power transistors of the power source is not generated. Similarly, the driver operates when the toggle switch (not shown) is restarted when the logic zero is applied to the restart input 43. This input allows you to create timing diagrams of the initial start-up without turning off the power source.

Claims (1)

Formulation Logic generator for switching the supply voltage on and off, comprising a first comparator connected by an inverting input to the first terminals of the first, second resistors and the first capacitor, a non-inverting input with the first the output of the third resistor, the first diode connected by the cathode to the second output of the second resistor, an NAND element connected by the first input to the first input of the former, the first output of which is connected to the first output of the fourth resistor and collectively. rum of the first transistor connected to the base with the first output of the fifth resistor, the second transistor connected to the collector with the second output of the driver and the first output of the sixth resistor, the base with the first output of the seventh resistor, the second comparator connected to the inverse input to the first terminals of the eighth and ninth resistors, a tenth resistor connected by a first terminal to a non-inverting input of a second comparator and a first terminal of an eleventh resistor, a twelfth and thirteenth resistors connected by first terminals, four the eleventh resistor connected by the first terminal to the anode of the second diode, the second terminal with the first terminals of the fifteenth resistor and the second capacitor, the third diode and the third capacitor, the sixteenth resistor connected by the first terminal with the power supply bus and the second terminals of the thirteenth, sixth and fourth resistors, the seventeenth resistor connected by a first terminal to a common driver bus and a common terminal of a second comparator, with a common terminal of a first comparator, second terminals of a first and second capacitor and emitters the first and second transistors, a positive power rail connected to the power terminals of the first and second comparators and the first terminals of the tenth and eighteenth resistors, characterized in that, for the sake of simplification, a third comparator, fourth, fifth and sixth diodes and an OR element are inserted into it HE, and the first, second and third inputs of the OR-HE element are respectively the second, third and fourth inputs of the driver, and the output is connected through the fourth and third diodes, respectively, with the second terminals of the eighth and ninth resistors, and not indirectly - with the second input of the NAND element, the third input of which is the fifth input of the driver, and the output is connected to the anodes of the first and fifth diodes, the cathodes of the sixth and second diodes, the anode of the sixth diode is connected to the second terminal of the first resistor, the cathode of the fifth diode is connected to the second the output of the fifteenth resistor, the first output of the third capacitor is connected to the inverting input of the second comparator connected to the first output with the third output of the former and the second conclusions of the eleventh and eighteenth resistors, second the seventh output of the seventeenth resistor is connected to the direct input of the second comparator, the inverting input of the third comparator is connected to the first output of the second capacitor, its non-inverting input and the first output are respectively connected to the second output and the first output of the twelfth resistor, the second output to the base of the second transistor, the first output of the first the comparator is connected to the second terminals of the third and sixteenth resistors, the second output to the base of the first transistor. the common driver bus is connected to the common terminal of the third comparator, the second terminal of the fifth resistor, the second output of the second comparator, the second terminal of the third capacitor and the second terminal of the seventh resistor, the positive power bus of the former is connected to the power terminal of the third comparator.