SU1647443A1 - Digital electricity meter for multiphase mains - Google Patents

Abstract

The invention relates to electrical measuring technology and can be used in the construction of high-precision digital devices for measuring electrical energy in a multiphase network. The aim of the invention is to improve the accuracy. The goal is achieved by introducing the scale converter (MP) 4, the second and third keys 24 and 25, the voltage converter VC converter 6, the combiner adder 7, two multipurpose registers 8, 18, generator 9, four counters 10, 11, 12, 17 , block 13, frequency selection, block 14, Form 041, and the interpolation of an impulse element 2И 15, two elements 2И-НЕ 21, 22, desc} j, a delay element 20, -input i-th element j И И НЕ 16, fier. , frequency, n controlled dividers 20 i ,. , 26.p frequencies (UDCH), n registers 27 1 ,. ., 27 p p differentiating circuits 28 1, 28 p n-input logic element p-OR 29, indication unit 30 Measurement of the energy of a multiphase network d. - "without structural parallelization, by the number of phases. The use of input-frequency knots allows you, by sending a polling of all phases of the total power network, while synchronization of switch B and PIC allows you to eliminate the influence of switching. emissions on the accuracy of the device. The high-speed selection of the transfer factors MP 4 and UDCH separately for each phase makes it possible to measure energy by phase with high accuracy. The device also contains n transformers 1.1, ..., 1.p voltage, n transformers 2.1 2.p current, the first key 3. 2 Cp. F-ly, 5 ill. Н§ Јь 2 4 WITH Schig1

Description

The invention relates to electrical measuring technology and can be used in the construction of high-precision digital devices for measuring electricity in a multiphase network.

The aim of the invention is to improve the accuracy of measuring electricity of a multi-phase network.

FIG. 1 is a block diagram of a digital multi-phase network electric power meter; in fig. 2 a-b shows block diagrams of a multiplier, a frequency selection unit and a filling pulse shaping unit, respectively; in fig. 3 and 4 - timing charts of the device; in fig.

5- characteristics of the multiplier.

The digital meter of electrical energy of a multiphase network contains input transformers 1.1, ..., 1, p voltage, input transformers 2.1. ..., 2.p current, first key 3, scale converter 4, multiplier 5, converter

6 voltage coded., Combinational adder 7, first multipurpose register 8, generator 9, first, second and third pilots 10-12, respectively, frequency selection unit 13, filling pulse shaping unit 14, logic element J. -L 15, logical element AND NOT 16, fourth counter 17; the second multipurpose register 18, the decoder 19, the element 20, the delay, the first and second logic elements 2Vi- HE 21 and 22, respectively, the frequency divider 23, the second and third key 24 and 25, the controlled dividers 26.126.p frequencies, registers 27.1, ... , 27.p, differentiating circuits 28.128.p, logical element

drank 19 and display unit 20.

Transformers 1.1, ..., 1.p voltage and transformers 2.12.p current connected to the first peak of the second n inputs of the key 3, respectively. The first output of the key 3 is connected to the first input of the multiplier 5, and the second output through the large-scale converter 4 is connected to the second input of the multiplier 5, the output of which is connected to the second input of the combination multipurpose register 8 via the voltage-to-voltage converter 6. The first output is connected to the first input of the combinational adder 7. The output of the generator 9 is connected to the recording input of the multipurpose register 8, the control input of the multiplier 5, to the clock input of the frequency selection unit 13, through a counter 11 - to the inputs of the write address and read address B of the multipurpose register 18 and to the control input of the key 25, as well as directly to the input of the counter 10, the first output of which is connected to the control input of the voltage converter 6 to the code, and the second output to the control key inputs 3 and 24, to the inputs of the first read address A of the multipurpose register

Ditch 8 and 18 to their input of the write address of the multipurpose register 8. The output of the frequency selection unit 13 is connected to the second input of the logical element 2I 15 through the block 14 to form the storage pulses, output

0 through which the counter 17 is connected to the inputs of the multipurpose register 18 and the logic element jH-HE 16, which is connected to the first inputs of the logic elements 2I-HE 21 and 22.

5 The first output A of the multipurpose register 18 is connected via the decoder 19 to the control input of the scaler 4, and its second output B via the registers 27.1, ..., 27.n to the control

0 inputs of controlled dividers 26.126.p

frequencies, respectively. The lowest bit of the second output In the multipurpose register 18 through the counter 11 is connected to the input frequency selection unit 13 frequency selection. The transfer path 5 of the combinational adder 7 is connected to the input of the key 24, the first output of which is controlled by the controlled frequency divider 2b.p and the differentiating circuit 28.p is connected to the first input of the logic element UL AND 29. The outputs of the key 24 from the second

 Go nth through controlled dividers 26.1 ....,

26. (p-1) frequencies and through differentiating

circuits 28.1, ..., 28, (p-1) are connected to the inputs

logic element drank 29 from the second to

5, respectively, the output of which is connected to the input of the display unit 30.

The outputs of the controlled dividers 26.1 26.p are connected to the corresponding inputs of the key 25 from the first to the fifth.

0 The first output of the switch 25 through the frequency divider 23 and the delay element 20 is connected to the reset inputs of the frequency selection unit 13, the filling pulse shaping unit 14 and the counter 17, and through the divider 23

5 frequencies - with the second input of the logic element 2I / I-HE 21, the output connected to the second input of the logic element 2И-НЕ 22, the output of the latter is connected to the recording input of the multipurpose register 18 and c (n + 1) -m

0 by the input of the unit 25, the outputs of which from the second to (n + 1) -th are connected to the inputs of the record registers 27.127, n respectively.

The multiplier 5 (FIG. 2a) contains an analog-to-digital converter 31 (ADC 31) and

5 multiplying digital-to-analog converter 32 (D / A converter 32). The second input of the multiplier 5 is connected via ADC 31 to the input of the DAC 32, the input of the reference voltage of which is connected to the first input of the multiplier 5, and the output is connected to the output of the multiplier .5, the control input

which is connected to the control input of the ADC 31.

The frequency selection unit 13 (UHF 13) (FIG. 26) comprises a fifth counter 33. an inverter 34, a second logic element 2I 35, a logic element ZI, and the first and second logic elements 2 OR 37 and 38, respectively. The clock input BVC 13 is connected to counter input 33, the first output of which is connected to the first outputs of logic elements 35 and 36, which are connected to the first and second inputs of logic element 37 by the outputs, the output of the latter is connected to the output of the UHF 13 and the first input of the logical element 38, the input of which is connected to the reset input of the high frequency 13, output - to the input of counter 33. Reset Enter frequency selection BVCH 13 is connected through an inverter 34 to the second input of NAND gate 35 and directly - to the third input member 36, the second input of which is connected to the second output of the counter 33.

The filling pulse shaping unit 14 (BFZI 14) (Fig. 2b) comprises a second delay element 39, a counter 40 sec. Of pre-installation and a counter distributor 41 of pulses. The clock input of the BFZI 14 is connected to the counting input of the counter 40 with a preset, the reset input of which is connected to the reset inputs of the counter-distributor 41 pulses and BFZI 14. The output of the BFZI 14 is connected to the counting input of the counter 41, with the transfer output of the counter 40 and through the elec - ment 39 delay - with the input of the record of the counter 40, the pre-installation of which is connected to the output of the counter 41.

The device works as follows. ..V

The operation of the digital electric energy meter blocks is synchronized by the output pulses of the frequency fiy of the generator 9, as well as by the codes on the second output of the control counter 10 and on the output of the control counter 11, which cyclically vary with the frequencies f2y and fsy, respectively. In addition, to control the start of the A / D converter 31 in multiplier 5 and voltage converter 6, a 2f2y pulse sequence from the first output of counter 11 is used.

, -Ј:, 0)

where z, q are integers, and 1 z q (therefore, fiy f2y f3y).

As a result, keys 3 and 24 are switched to the polling frequency fay, and

also the cyclic change of the write address of the multipurpose register 8 and the readout addresses A of the multipurpose registers 8 and 18, and with a lower interrogation rate (the switch is the key 25 and the cyclic change of the write addresses and the readout B of the multipurpose register 18.

The multipurpose registers 8 and 18 are devices that write input information on the leading edge of the signal at the write input to the cell with the address set at the input of the write address, and read information to outputs A and B from the cells whose addresses are determined codes at the inputs of the read address A and B, respectively. In this case, the number of cells used in registers 8 and 18 is determined by the number of phases n in the network. The multipurpose register 8, in conjunction with the combinational adder 7, forms an n-phase accumulating adder, and the multipurpose register 18 is used in the proposed digital meter for receiving, storing and reading the generated MF code values determining the gain factors .1К4.n scale converter 4 and division factors frequencies K26.1 K2b.p controlled dividers

26.1, ..., 26.p frequencies separately for each phase. Moreover, for each Fth phase, these coefficients are determined by the expression K4. F K26. F. (where Mp is an integer) and automatically matched in such a way that the multiplier 5 and the voltage-to-voltage converter 6 continuously operate in a narrow optimal portion of their performance, regardless of the magnitude of the phase currents.

Transformer Output

1.1 1.p voltage and 2.1 2.p current with

The frequency f2y is cyclically polled with the help of key 3. With the same frequency f2y, the amplification factors YumKz.p of the scale converter 4 change, which for the Fth phase come from the Fth cell of the multipurpose register 18 to its output A and then through the decoder 19 - to the control input of the input scale converter. The time T r 1 / f2y of connecting the voltage and current signals of the F-th phase to the inputs of multiplier 5 is called the clock cycle, and the time of the polling time n / f2y with the key 3 of all n phases is the measurement cycle.

Thus, during a short-term connection of the voltage and current of the Fth phase, the analog sample of the instantaneous power Pp (i) is formed at the output of the multiplier 5 at the ith cycle.

PF (1) - U.F K2.F K4F K5

t „

bS uK-sln (-S-v4 + vV) x

v 1 | h

fK-slnC- -vl + V), (2)

where K t F, K2.F, K4 F, Ks are transmission coefficients, the numbering of which coincides with the numbers of the corresponding blocks;

l l 1

U FI I F - amplitude values of voltage and current of the v-th harmonic of the F-th phase, with 1, N - the ratio of the frequency f2y to the frequency

1 first harmonic of input signals, N f2y / fi;

    phase shifts of voltage and current of the Fth phase of the Vth harmonic with respect to the transition of the voltages of the first phase of the first harmonic.

The control pulses from the first output of the counter 10 foul at the beginning of the i-th cycle of the A / D converter 31 multiplier 5 and voltage converter 6 to code. Therefore, at the end of the i-ro measurement cycle, when the Fth phase is connected, the output code Pp (i) of the instantaneous power is generated at the output of the converter b, which is stored at its output for the entire next (i + 1) -ro cycle. During i-ro, the same output of the voltage converter 6 to the code stores the instantaneous power code P (F-1) 0-1 of the previous phase, which is fed to the input of the n-phase accumulating adder consisting of adder 7 and register 8 The multipurpose register 8 is clocked at the write input by the output pulses of the generator 9 at a frequency fiy that is Z times the frequency f2y. In this case, the recording and reading in the multipurpose register 8 is carried out through the cell number F, which is determined by the corresponding code at its inputs of the write address and read address A, which also goes to the control input of the key 24.

Thus, during the 1st measurement cycle when connected with the key 3 signal-. catching the voltage and current of the F-th phase in the F-th cell of the multipurpose register 8 with a high frequency fiy is summed up the code value of the sample P (F-i) (l-1) (F-1) of the F-th phase, formed at the end of the previous cycle

SF (I) Z Kl F K2 F K4F K5 Kb, 2 U K Sln (-lЈv (l-1) + V1 uF)

V 1

IVF

In

sin ((i-1) + vV). (3)

five

0

five

0

five

0

five

where Sp (i) is the sum of the sampled code values Q of the power P (F-1) (H), which were summed Z times during the 1st cycle through the Fth cell of the n-phase accumulating adder;

KB - the transfer coefficient of the Converter 6.

As a result, at the output of the transfer of the adder 7 during the 1st measurement cycle with a frequency proportional to the value of P (Fi) (i-1), a burst of pulses is formed, which is connected by a key 24 through the corresponding controlled divider 26. (F-1 ) frequencies and a differentiating circuit 28. (F-1} to the (P-1) -th input of the element PILI 29 and accumulates in the display unit 30. Such high-frequency clocking of the n-phase accumulating adder allows a much higher speed when selecting transfer coefficients

converter 4 and dividers 26.126.

The gains of the scale converter 4 and the controlled divider 26.F frequencies for any Fth phase are equal, therefore the average frequencies of the pulses at the outputs of the controlled dividers 26.1, ..., 26.n are the frequencies of single-frequency "but determine the amount of electricity corresponding to phases. Hence, along with the total value of the n-phase electrical energy generated in the display unit 30, it is possible to measure the electrical energy of the individual phases with high accuracy.

Thus, over L measurement cycles, the display unit 30 of the proposed digital meter will receive the number of EN (L) pulses proportional to the measured electricity of the multiphase network in accordance with the expression

L n m

Em 00 2 -X -2 KI.F-K2.F-K4F

 F 1 V 1

50

KB: KB K, 8 26 F

uЈ-sln (4j- (nЈ + F) + Vi /)

In

| Ј.S | n (- | Ј (nt + F) VV, F), (3)

Where Ј.- is the cycle number;

Kb, K, 8, K26F - transfer coefficients of the corresponding block numbering.

Consider briefly the process of selecting the transmission coefficients, the time of which

determined for each of the phases by a Tzu 1 / fay period.

The output pulses of the generator 9 with frequency fiy arrive at the clock input of the high frequency 13, which, depending on the single or zero signal at the frequency selection input, produces at its output pulses with frequency fiy / x or fsy 2fiy / 3x 2f4y / 3, respectively, (where x is integer). These pulses arrive at the clock input of the BFZI 14 and cause the formation at its output of a binary sequence of filling pulses, the arrival time of each next one of which is twice the previous one (Fig. 3, b).

During the time Tzu, the pulse bursts from the output of the controlled divider 26.F of the frequency of one of the phases, the passage through the switch 25 and the controlling divider 23 of the frequency, are converted into a sequence of pulses with a relatively uniform period. Next, these pulses with a single output signal of the element 16 through the logic elements 21 and 22 are fed to the input of the record of the multipurpose register 18 and through the key 25 to the record of the corresponding register 27, F. As a result, during each period of the output pulses of the splitter 23 frequencies proportional to the energy of the Fth phase, the output pulses of the BFZI 14 accumulate in the counter 17. At the end of each pulse period, the output code MF of the counter 17 is written to the Fth the multipurpose register cell 18 and output B to the corresponding register 27.F, after which, for synchronization purposes, blocks 13 and 14 and counter 17 are reset and the whole process is repeated again. In this case, the address of the cell F is determined by the code F, which arrives at the inputs of the write address and read address B with the frequency tzu, (q / z) times lower than the frequency f2y. Hence, the frequency of reading of the gain factors for output A and the division factors for output B in the multipurpose register 18 is different and differs (q / z) times.

Logic element 16 is required to reliably set the maximum gain factor K4.F for the Fth phase with zero or minimum load. In this case, the period of the output pulses of the divider is large, and when the maximum code (all ones) appears at the output of the counter 17, the drop to zero of the output signal of the logic element JI / 1-HE blocks the element 15, prohibiting further counting in the counter 17, as well as through elements 21 and 22, writes this maximum code, Mrtach, to the multipurpose register 18 and, through its output B, to the corresponding register 27.F.

With variations in the load and non-uniformity of the output pulses of the frequency divider 23, malfunctions and an unstable selection of the transfer coefficients of the converter 4 and the divider 26.1 can occur, .., 26.p. To eliminate this phenomenon in the proposed

0 device 12 and block 13 are entered. If at one output frequency of the RFI 13, the low-order bit of output B of the multipurpose register 18 fails, then the output logic level of the counter 12

5 is changed to the opposite, which also changes the output frequency of the UHF 13 cha i, p ". Therefore, the faults and the unstable p 10%% v are eliminated completely.

The multiplier 5 (Fig 2 a) h p

0 multiplication of the phase code, - the corresponding analog voltage extrusion by the joint f ,,, and the coding of the A / D converters 31 and D / A 3 Simulation of the multiplier 5 occurs according to

5 control input

BVCh 13 (FIG. 2 b) produce dolepi x times by counter 33 of the input after TV, TV, of frequency pulses f: rgprog.h at the outputs of logic elements 2) i

0 36 frequency signals or fsvCooTp -r, but depending on the signal level n, ino i i the frequencies at the input of the inverter 34, n jvuee output to the output of the control, with through element 2IL 37 Pulse per g

5 de reset BWC 13, passing through 5, ment 38 to the input reset of the counter is performed by synchronizing this b i k.

Consider the work BFZI 14 (fmg 2 G4

0 The reset signal sets the counters 0, 41 to the zero state. After that, ir,: during the course of the counter 40 with the advance (-; a pulse is formed at the counting input of the counter 41, distribute 5 liters of pulses and with some delay - to the recording input of the counter 40. As a result, the counter 40 is preset to the 2 ° state. Each pulse arriving at the counting input of counter 40 causes the unit to be subtracted from the number recorded during the preset.When zero reaches the transfer output of the counter 40 with the preset, a pulse appears again, as a result of which seniority output of the counter 41 by the pulse distributor signal is a logic one, and the counter 40 predustanavlivaets in state 21. Then the process is repeated as long as the reset inputs of counters 40 and 41 are not received

the next pulse, which sets them to the zero state.

Thus, each pulse from the output of the frequency divider 23, coming through the delay element 20 to the reset input of the BFZI 14, causes the appearance of a series of pulses at the output of the latter. At the same time, the time intervals between the moment of resetting of the BFZI 14 and each subsequent pulse appearing at its output double.

FIG. 3 a, b, c, d shows the time diagrams of the signals at the clock input of the BFZY 14, the output of the BFZI 14, the output of the frequency divider 23 and the output of the delay element 20, respectively. The number of pulses received from the BFZI 14 into the counter 17 during the time interval between two reset pulses at their reset inputs is the number Mp, which is then recorded in the Fth cell of the multipurpose register 18, and the values of the coefficients K4.F and Кзб are determined .P for the corresponding phase.

FIG. 4 shows the dependence of the number Mp on the period of the output signal of the frequency dividers. As can be seen from the graph, due to the functioning of the frequency selector, the characteristic has a hysteresis for each MF value, which improves the reliability and accuracy of the device due to the absence of false positives of the circuit. FIG. 4 That is the minimum threshold value of the period of the output signal of the frequency divider.

Thus, the device improves measurement accuracy,

The measurement of the electricity of a multiphase network in the proposed digital electricity meter is achieved without parallelizing the block diagram by the number of phases of the network under study, which would lead to an increase in hardware costs. The use of the introduced digital nodes allows to measure the total electric power of the network by a quick interrogation of all phases, while synchronizing the multiplier and the voltage converter into the code eliminates the effect of switching surges on the accuracy of the device. The high-speed selection of the transmission coefficients of the scale converter and controlled frequency dividers separately for each phase makes it possible to measure phase-phase energy with high accuracy. The construction of most blocks based on digital elements allows, if necessary, to transfer this structure to LSI, since the analog adjustments and adjustments in the implementation of the device are practically absent.

The use of the invention makes it possible to increase the measurement accuracy in comparison with the known multiphase electricity meters due to the fact that regardless of the magnitudes of the currents in each of the n phases (which can generally differ significantly from each other), the multiplier 5 in the proposed digital meter operates on a narrow linear plot of its working characteristics, not exceeding three (Fig. 5, where 42 and 43 - is the ideal and real performance characteristics of the multiplier):

nH Ufe (max) 3 when

U smart (min) 1 mind1n5 -const.,

With MF 7, in the proposed device, the full dynamic range of the HF of the currents in each of the phases is

pax

HF

U smart (max) U smart 5 (min)

M

3 27 384

(11um2n5 - signals at the first and second inputs of the multiplier, proportional to the phase voltage and current) with an error of y determined by Hrmn 3. At the same time, in the prototype, to achieve the same range, the multiplier should work in the range 3, which inevitably leads to an increase in its multiplicative error and an increase in the nonlinearity errors and, consequently, to a decrease in accuracy. In the well-known multiphase electricity meters for the same reasons, achieving high accuracy is difficult because of the non-ideal performance characteristics of the multipliers (Fig. 5).

Claims (3)

Claim 1. Digital multiphase network electrical energy meter containing n voltage transformers, n current transformers, a multiplier and a key, wherein the outputs n of current transformers and n voltage transformers are connected to the information inputs of the key, characterized in that , a scale converter, a controlled frequency divider, a display unit, second and third keys, a voltage converter into a code, a combination adder, two multipurpose registers, a generator, h are entered into it. Four counters, a frequency selection unit, a filling pulse shaping unit, a logical element 2I, two logical elements 2I-NOT, a decoder, a delay element, j-input logic element IS-NOT, frequency divider, n controllable frequency dividers, n registers, n differentiating circuits, and n-vsdovoy logical element n-OR, the first output of the first key connected to the first input of the multiplier, and the second output through the scale converter is connected to the second input of the multiplier, the output of which is connected to the second input of the combinational adder via the voltage-to-voltage converter, which is connected to the input of the first multipurpose register and the first input to the first output of the first multiplex The second register, the generator output is connected to the write input of the first multipurpose register and to the clock input of the frequency selector, through the second counter to the write address addresses and the second read address of the second multipurpose register and to the control input of the third key, as well as with the input of the first counter, the first output of which is connected to the control inputs of the multiplier and the voltage converter into the code, and the second output to the control inputs of the first and second keys and the inputs of the first read address of the first and second and the input address of the first multipurpose register entry, the output of the frequency selection block is connected to the second input of the second multipurpose register through the fourth counter of the logic element 2I, the output of which through the fourth counter is connected to the input of the second multipurpose register NOT, which output is connected to the first inputs of the logic element 2I, the first and second logic elements 2I-NOT, the first output of the second multipurpose register is connected to the control input through a decoder m of the large-scale converter, and its second output through n registers with control inputs and controlled frequency dividers, respectively, the lower bit of the second output of the second multipurpose register through the third counter is connected to the frequency select input of the frequency selector output of the combinational adder is connected to the second input key, whose outputs through n controlled frequency dividers and through n differentiating circuits are connected to the inputs of the logic element p OR, respectively, whose output is connected to the input The display locator, the p outputs of the controlled frequency dividers are connected to the corresponding n first inputs of the third key, the first output of which through the frequency divider and the delay element is connected to the reset inputs of the frequency selection unit, the filling pulse shaping unit and the fourth counter, the output of the frequency divider also connected to the second input of the first logic element 2I-NOT, the output of which is connected to the second input of the second logic element 2I-NOT, the output of which is connected to the recording input of the second multipurpose register and c (p +1) -th input of the third key, the outputs of which from the second to (n + 1) -th are connected to the inputs of the recording registers from the first to the n-th, respectively. 2. The meter according to claim 1, of which is that the frequency selection unit contains a fifth counter, an inverter, a second logic element 2I, a logic element ZI and doses of the logic element 2IL, and the clock input the frequency selector is connected to the counting input of the fifth counter, the first output of which is connected to the first inputs of the second logic element 2I and the logic ZI element, the outputs of which are connected to the first and second inputs of the first logic element 2IL And which output is connected to the output of the selection block frequencies and to the first approach The second logic element 2ILI, the second input of which is connected to the input reset frequency selection block, and the output - to the reset input of the first counter, frequency selection input w. Frequency selection wiring is connected via an inverter to the second input of the second logic element 2I and directly to the third input of the element ZI, the second input of which is connected to the second output of the fifth counter. 3. Pop meter 1, so that the block for forming filling pulses contains a second delay element, a counter with presetting and a counter-distributor of pulses, the clock input of the block for forming filling pulses connected to the counter input of the counter with preset, the reset input of which is connected to the reset inputs of the pulse distributor and the filling pulse shaping unit, the output of which is connected to the counting input of the pulse distributor, with the transfer transfer counter a preset and through the second delay element - a counter input recording preset, the preset input of the counter-kotorogopodklyuchenkvyhodu distributor pulses. T,  B / g, l 7, l, g, d F / g U6 A UMN3 I Smart5 (min) U M Um5 (mox.) (& US.5