SU1646056A1 - Delta-coder - Google Patents

Abstract

The invention relates to telecommunications and is intended to convert analog signals to digital form. The aim of the invention is to expand the dynamic range of the converted signals. To achieve this goal, a delta encoder containing a comparator, a trigger, a symbol pack selector, and a digital integrator were additionally introduced, multiplying the PAP, the digital filter and the inverter block. The use of dual adaptation device, i.e. Simultaneous control of the comparator input level and quantization step size in accordance with the parameters of the signal being converted allows, in addition to improving the quality of the conversion, to reduce the demands on the characteristics of the element base. 2 Il.

Description

The invention relates to telecommunications, is designed to convert analog signals into digital form and can be used in specialized electronic PBX small capacity and medium capacity, as well as in other areas of electronic technology, where high-quality analog-digital conversion of signals is required.

The aim of the invention is to expand the dynamic range of the converted signals.

FIG. 1 shows a flow chart of a delta coder; in fig. 2 - timing diagrams illustrating the principles of operation of its individual nodes.

Delta encoder contains multiplying digital-to-analog converter (PAP) 1, comparator 2, trigger 3,

a selector of 4 packs of symbols, a digital syllabic filter 5, a digital integrator 6 and a block of 7 inverters. The set of arithmetic logic unit (ALB), the first buffer register and the PAP of the prototype device is a digital integrator, the information input bus of which is the first group of inputs of the arithmetic unit, the output is the PAL output, the control input is the control input arithmetic the logical block, and the gate input the gate input of the first buffer register, the set of the shift register, the first and second AND elements, and the OR element in the prototype is a selector of packs of symbols, at the output of which th (yield packs selector is an output of OR) logical units FormiO5 4. On O5 SP

Yes

if there are two or more element packs in the delta-modulated (DM) stream (the following subgroups of the same type characters), the information and gate inputs of the pack selector are the information and gate entries of the shift register, respectively.

As a digital syllabic filter, in particular, a digital DM filter can be used. Anna-- this filter can be implemented in a variety of ways, for example, with a shift register, a set of buffer registers with a parallel record and an adder, and The filter receives a digital DM stream, which with the arrival of clock pulses on the register gating input fills its bits. Each bit of the DM stream goes to one of the information inputs of the corresponding buffer register, all the other inputs s which are grounded. The use of certain inputs of the buffer registers depends on the specific requirements for the characteristics of the digital syllabic filter. The characteristics of the filter, in turn, are determined with the specific conditions of use of the delta coder, as well as the type and parameters of the input signal

The appearance of logical units in the bits of the shift register causes the formation of given binary numbers at the outputs of the corresponding buffer registers. By summing up the adder, these numbers form the response of the digital filter to the input action.

The delta coder works as follows.

The analog input signal U (t) is fed to the input of the reference voltage of multiplying DAC 1 and appears at its output, weakened K times. The attenuation coefficient K is determined by a binary code combination at the information inputs of multiplying PAT 1:

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P ieh

Ada

2G

g is the multiplier bit depth

DAC 1;

A. - code combination on informational inputs of the multiplying PAP 1, presented

$ 0 5 0

, 0

five

0

five

in decimal notation.

If we assume that at the moment of the start of operation the binary code combination at the output of the digital syllabic filter 5 corresponds to the number 0 in the decimal number system (the combination 000 ... 000), then the inverted combination of inverter block 7 (111 ... 111) on the information inputs of the multiplying PAP 1 correspond to the number -1 in the decimal number system, and therefore, the input signal U (t) is switched to the output of the multiplying PAP with the maximum transmission coefficient.

This signal is fed to the input of comparator 2, where it is compared with the approximating signal and (O, present at the other input of comparator 2 ". In case U (t) U (t), a logical zero is formed at the output of comparator 2. For U (t) The LU (t) comparator 2 outputs a logical unit.The two-level signal from the output of the comparator 2 is fed to the information input of the trigger 3, to the gate input of which the clock pulses from the synchronization bus are supplied. With the arrival of each clock pulse, the logic potential present on the information input of the trigger Gera 3 is recorded in it, appears at its output and is maintained there at least until the next pulse of the clock sequence arrives. Thus, bits of the output DM signal are formed, each of which goes to the output of the device, and also simultaneously to the information the input of selector A of the bursts of symbols and the control input of the digital integrator 6. With the arrival of successive clock pulses, a fragment of the digital DM stream is sequentially recorded into the selector of 4 packs of symbols and analyzed last for the presence of two or more elemental packs. The principle of generating the output signal of selector A of bursts of symbols when using a two-bit (for conspicuity) shift register in it is illustrated by timing diagrams for League. 2

The signal Y (t) from the output of the selector A of packets of symbols (Fig. 1) is fed to the information input of the digital syllable filter 5, averaged by it

and comes in the form of a code combination proportional to the average density of the digital signal Y (t), to the information inputs of the digital integrator 6.

The supply to the control input of the digital integrator of bits of the digital DM signal v (t) (with simultaneous supply of clock pulses through its strobe input) causes the approximate voltage U (t) at the output of the digital integrator 6 to change (or increases or decreases) in each operation cycle of the device by an amount proportional to the binary code combination present at the time of arrival of the clock pulse at the information inputs of the integrator 6, moreover, if the current bit of the DM stream corresponds to skom zero, there is a reduction approximating voltage U (t), in the case, if the current bit Y (t) l, there is an increase in the voltage U (t).

Obviously, the feedback realized in this way (Fig. 2) causes the approximate voltage U (t) to always be changed in such a way as to reduce the difference {U (t) - U (t) | i.e. voltage (t) will approximate the input signal U (t).

In order to improve the quality of the conversion (decrease the difference between U (t) and U (t) and expand the dynamic range), the adaptation of the parameters (companding) is introduced into the device.

It is known that two-, three-, and more elemental bursts are formed in a digital DM signal when the approximate voltage U (t) does not catch up with the rapidly changing input signal U (t) for two, three, or more cycles. The presence of a large number of such fragments (multi-element packs) in the DM signal Y (t) over a long period of time indicates the need to change the ratio of the amplitude (level) of the input signal of comparator 2 and the quantization step.

This ratio can be changed in two ways: by affecting the quantization step size and by adjusting the input signal level of the comparator 2 (the signal coming

0

five

at its first entrance). The device uses both possibilities of such regulation, which is made as follows. The code combination from the output of the digital syllable filter 5, the value of which is proportional to the average density of the digital DM stream (therefore, the amplitude and frequency of the input signal U (t), goes to the information inputs of the digital integrator 6 and also inverted by the inverter unit 7 to the information inputs of the multiplying NAL 1 o With this switch on, the quantization step size with which the digital integrator 6 produces an approximat input cell crease

the frequency of the input signal, and the coefficient of transmission of the multiplying GAL 1 (at the input of the reference voltage) is inversely proportional to these values. As a result, a highly efficient companding is performed in the device, which leads to an expansion of the dynamic range of the converted signal. Any increase in the slope of the input signal U (t) leads to an increase in the binary code combination at the output of the digital syllabic filter 5, and therefore to an increase in the step of approximating voltage U (t), reducing the signal level at the input of the comparator 2 and stabilizing the signal-to-quantization noise ratio that is equivalent to expanding the dynamic range of the converted signals.

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Claims (1)

Invention Formula A delta encoder containing a comparator, the output of which is connected to the information input of the trigger, output 5 of which is the output bus and connected to the information input of the symbol pack selector and the control input of the digital integrator, the output of which is connected to the first input of the comparator, and the gate input is combined with The gate inputs of the trigger and the selector of symbol packs are a sync bus, which is characterized by the fact that, in order to expand the dynamic range of the converted signals, a digital layer is inserted into it Marketing Filter, power inverters and multiplies tsif- roanalogovy converter pri0 five than the output of the symbol pack selector is connected to the information input of a digital syllabic filter, the gate input of which is a synchronization bus, and the outputs are connected to the corresponding information inputs of a digital integrator directly and through an inverter unit with the corresponding information inputs of a multiplying digital analog converter, the output of which is connected to the second the input of the comparator, and the input of the reference voltage is the input bus c4 ), U (il 1 , n n n,